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  • Embedded system for biometric online signature verification

     Lopez Garcia, Mariano; Ramos Lara, Rafael Ramon; Miguel Hurtado, Oscar; Cantó Navarro, Enrique
    IEEE transactions on industrial informatics
    Vol. 10, num. 1, p. 491-501
    DOI: 10.1109/TII.2013.2269031
    Date of publication: 2014-02-01
    Journal article

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    This paper describes the implementation on field-programmable gate arrays (FPGAs) of an embedded system for online signature verification. The recognition algorithm mainly consists of three stages. First, an initial preprocessing is applied on the captured signature, removing noise and normalizing information related to horizontal and vertical positions. Afterwards, a dynamic time warping algorithm is used to align this processed signature with its template previously stored in a database. Finally, a set of features are extracted and passed through a Gaussian Mixture Model, which reveals the degree of similarity between both signatures. The algorithm was tested using a public database of 100 users, obtaining high recognition rates for both genuine and forgery signatures. The implemented system consists of a vector floating-point unit (VFPU), specifically designed for accelerating the floating-point computations involved in this biometric modality. Moreover, the proposed architecture also includes a microprocessor, which interacts with the VFPU, and executes by software the rest of the online signature verification process. The designed system is capable of finishing a complete verification in less than 68 ms with a clock rated at 40 MHz. Experimental results show that the number of clock cycles is accelerated by a factor of x4.8 and x11.1, when compared with systems based on ARM Cortex-A8 and when substituting the VFPU by the Floating-Point Unit provided by Xilinx, respectively.

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    Fast self-reconfigurable embedded system on Spartan-3  Open access

     Cantó Navarro, Enrique; Fons, Mariano; Fons, Francesc; Lopez Garcia, Mariano; Ramos Lara, Rafael Ramon
    Journal of universal computer science
    Vol. 19, num. 3, p. 301-324
    DOI: 10.3217/jucs-019-03-0301
    Date of publication: 2013-02
    Journal article

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    Many image-processing algorithms require several stages to be processed that cannot be resolved by embedded microprocessors in a reasonable time, due to their high-computational cost. A set of dedicated coprocessors can accelerate the resolution of these algorithms, although the main drawback is the area needed for their implementation. The main advantage of a reconfigurable system is that several coprocessors designed to perform different operations can be mapped on the same area in a time-multiplexed way. This work presents the architecture of an embedded system composed of a microprocessor and a run-time reconfigurable coprocessor, mapped on Spartan-3, the low-cost family of Xilinx FPGAs. Designing reconfigurable systems on Spartan-3 requires much design effort, since unlike higher cost families of Xilinx FPGAs, this device does not officially support partial reconfiguration. In order to overcome this drawback, the paper also describes the main steps used in the design flow to obtain a successful design. The main goal of the presented architecture is to reduce the coprocessor reconfiguration time, as well as accelerate image-processing algorithms. The experimental results demonstrate significant improvement in both objectives. The reconfiguration rate nearly achieves 320 Mb/s which is far superior to the previous related works.

    Many image-processing algorithms require several stages to be processed that cannot be resolved by embedded microprocessors in a reasonable time, due to their high-computational cost. A set of dedicated coprocessors can accelerate the resolution of these algorithms, alt hough the main drawback is the area needed for their implementation. The main advantage of a reconfigurable system is that several coprocessors designed to perform different operations can be mapped on the same area in a time-multiplexed way. This work presents the architecture of an embedded system composed of a microprocessor and a run-time reconfigurable coprocessor, mapped on Spartan-3, the low-cost family of Xilinx FPGAs. Designing reconfigurable systems on Spartan-3 requires much design effort, since unlike higher cost families of Xilinx FPGAs, this device does not officially support partial reconfiguration. In order to overcome this drawback, the paper also describes the main steps used in the design flow to obtain a successful design. The main goal of the presented architecture is to reduce the coprocessor reconfiguration time, as well as accelerate image-processing algorithms. The experimental results demonstrate significant improvement in both objectives. The reconfiguration rate nearly achieves 320 Mb/s which is far superior to th e previous related works.

  • Real-time speaker verification system implemented on reconfigurable hardware

     Ramos Lara, Rafael Ramon; Lopez Garcia, Mariano; Canto Navarro, Enrique Fernando; Puente Rodriguez, Luis
    Journal of Signal Processing Systems
    Vol. 71, num. 2, p. 89-103
    DOI: 10.1007/s11265-012-0683-5
    Date of publication: 2013-05-01
    Journal article

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    Nowadays, biometrics is considered as a promising solution in the market of security and personal verification. Applications such as financial transactions, law enforcement or network management security are already benefitting from this technology. Among the different biometric modalities, speaker verification represents an accurate and efficient way of authenticating a person¿s identity by analyzing his/her voice. This identification method is especially suitable in real-life scenarios or when a remote recognition over the phone is required. The processing of a signal of voice, in order to extract its unique features, that allows distinguishing an individual to confirm or deny his/her identity is, usually, a process characterized by a high computational cost. This complexity imposes that many systems, based on microprocessor clocked at hundreds of MHz, are unable to process samples of voice in real-time. This drawback has an important effect, since in general, the response time needed by the biometric system affects its acceptability by users. The design based on FPGA (Field Programmable Gate Arrays) is a suited way to implement systems that require a high computational capability and the resolution of algorithms in real-time. Besides, these devices allow the design of complex digital systems with outstanding performance in terms of execution time. This paper presents the implementation of a MFCC (Mel-Frequency Cepstrum Coefficients)¿SVM (Support Vector Machine) speaker verification system based on a low-cost FPGA. Experimental results show that our system is able to verify a person¿s identity as fast as a high-performance microprocessor based on a Pentium IV personal computer.

    Nowadays, biometrics is considered as a promising solution in the market of security and personal verification. Applications such as financial transactions, law enforcement or network management security are already benefitting from this technology. Among the different biometric modalities, speaker verification represents an accurate and efficient way of authenticating a person’s identity by analyzing his/her voice. This identification method is especially suitable in real-life scenarios or when a remote recognition over the phone is required. The processing of a signal of voice, in order to extract its unique features, that allows distinguishing an individual to confirm or deny his/ her identity is, usually, a process characterized by a high computational cost. This complexity imposes that many systems, based on microprocessor clocked at hundreds of MHz, are unable to process samples of voice in real-time. This drawback has an important effect, since in general, the response time needed by the biometric system affects its acceptability by users. The design based on FPGA (Field Programmable Gate Arrays) is a suited way to implement systems that require a high computational capability and the resolution of algorithms in real-time. Besides, these devices allow the design of complex digital systems with outstanding performance in terms of execution time. This paper presents the implementation of a MFCC (Mel-Frequency Cepstrum Coefficients)—SVM (Support Vector Machine) speaker verification system based on a low-cost FPGA. Experimental results show that our system is able to verify a person’s identity as fast as a high-performance microprocessor based on a Pentium IV personal computer.

  • Ataques por canal lateral sobre el algoritmo de encriptación AES implementado en MicroBlaze.

     Lumbiarres López, Rubén; Lopez Garcia, Mariano; Cantó Navarro, Enrique
    Jornadas sobre computación reconfigurable y aplicaciones
    p. 105-112
    Presentation's date: 2013-09-19
    Presentation of work at congresses

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    Este artículo presenta un procedimiento simple para la obtención de la clave criptográfica del algoritmo AES ejecutado sobre MicroBlaze. La clave se obtiene analizando la correlación estadística que existe entre ésta y el consumo del dispositivo hardware que ejecuta el propio algoritmo. El trabajo también muestra como las contramedidas clásicas de enmascarado del texto plano son únicamente eficientes frente ataques de primer orden. Los resultados experimentales muestran diferentes ataques realizados sobre varios bloques del algoritmo, y concluyen que es posible obtener la clave criptográfica tomando un número de trazas de corriente inferior a 40.

    Este artículo presenta un procedimiento simple para la obtención de la clave criptográfica del algoritmo AES ejecutado sobre MicroBlaze. La clave se obtiene analizando la correlación estadística que existe entre ésta y el consumo del dispositivo hardware que ejecuta el propio algoritmo. El trabajo también muestra como las contramedidas clásicas de enmascarado del texto plano son únicamente eficientes frente ataques de primer orden. Los resultados experimentales muestran diferentes ataques realizados sobre varios bloques del algoritmo, y concluyen que es posible obtener la clave criptográfica tomando un número de trazas de corriente inferior a 40.

  • Universal access through biometrics in mobile scenarios

     Sanchez-Reillo, Raul; Blanco-Gonzalo, Ramon; Liu-Jimenez, Judith; Lopez Garcia, Mariano; Cantó Navarro, Enrique
    International Carnahan Conference on Security Technology
    Presentation's date: 2013-10-08
    Presentation of work at congresses

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    The main aim of this paper is the development of a new technology for biometric recognition that allows safe and secure access to universal services such as credit card payment, ATMs, access control, border control, etc. The technology being developed is very generic and easily adaptable to the specific particularities of disabled people; a collective that represents an important proportion of current population (e.g. about the 9% of the total Spanish population).

    The main aim of this paper is the development of a new technology for biometric recognition that allows safe and secure access to universal services such as credit card payment, ATMs, access control, border control, etc. The technology being developed is very generic and ea sily adaptable to the specific particularities of disabled people; a collective that represents an important proportion of current po pulation (e.g. about the 9% of the total Spanish population).

    Postprint (author’s final draft)

  • TEC2012-38329-C02-02 - ACCESO UNIVERSAL MEDIANTE RECONOCIMIENTO BIOMETRICO EN ENTORNOS MOVILES - UPC

     Ramos Lara, Rafael Ramon; Lopez Garcia, Mariano; Gaya Suñer, Pedro Francisco; Cantó Navarro, Enrique
    Competitive project

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    Hardware-software co-design of an iris recognition algorithm  Open access

     Lopez Garcia, Mariano; Daugman, J.; Cantó, Enrique
    IET information security
    Vol. 5, num. 1, p. 60-68
    DOI: 10.1049/iet-ifs.2009.0267
    Date of publication: 2011-04-07
    Journal article

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    This paper describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32- bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared to a conventional software-based application. Experimental results show that with a clock speed of 40 MHz, an IrisCode is obtained in less than 523 ms from an image of 640x480 pixels, which is just 20% of the total time needed by a software solution running on the same microprocessor embedded in the architecture.

  • FPGA-based personal authentication using fingerprints

     Fons, Mariano; Fons Lluis, Francesc; Cantó, Enrique; Lopez Garcia, Mariano
    Journal of Signal Processing Systems
    Vol. 66, num. 2, p. 153-189
    DOI: 10.1007/s11265-011-0629-3
    Date of publication: 2011-10-15
    Journal article

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  • Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications

     Fons Lluis, Francesc; Fons LLuis, Mariano; Cantó Navarro, Enrique; Lopez Garcia, Mariano
    Journal of real-time image processing
    num. Special Issue, p. 1-23
    DOI: 10.1007/s11554-010-0186-1
    Date of publication: 2011-01-14
    Journal article

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    This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard architecture able to enhance the performance-cost trade-off delivered by other alternatives nowadays in the market like general-purpose multi-core processors. Our approach, sustained by hardware/software (HW/SW) co-design and run-time reconfigurable computing, is synthesizable in SRAM-based programmable logic. As proof-of-concept, a run-time partially reconfigurable field-programmable gate array (FPGA) is addressed to carry out a specific application of high-demanding computational power such as an automatic fingerprint authentication system (AFAS). Biometric personal recognition is a good example of compute-intensive algorithm composed of a series of image processing tasks executed in a sequential order. In our pioneer conception, these tasks are partitioned and synthesized first in a series of coprocessors that are then instantiated and executed multiplexed in time on a partially reconfigurable region of the FPGA. The implementation benchmark of the AFAS either as a pure software approach on a PC platform under a dual-core processor (Intel Core 2 Duo T5600 at 1.83 GHz) or as a reconfigurable FPGA co-design (identical algorithm partitioned in HW/SW tasks operating at 50 or 100 MHz on the second smallest device of the Xilinx Virtex-4 LX family) highlights a speed-up of one order of magnitude in favor of the FPGA alternative. These results let point out biometric recognition as a sensible killer application for run-time reconfigurable computing, mainly in terms of efficiently balancing computational power, functional flexibility and cost. Such features, reached through partial reconfiguration, are easily portable today to a broad range of embedded applications with identical system architecture.

  • Deployment of run-time reconfigurable hardware coprocessors into compute-intensive embedded applications

     Fons Lluis, Francesc; Fons LLuis, Mariano; Cantó Navarro, Enrique; Lopez Garcia, Mariano
    Journal of Signal Processing Systems
    Vol. 66, num. 2, p. 191-221
    DOI: 10.1007/s11265-011-0607-9
    Date of publication: 2011-08-10
    Journal article

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  • Aportaciones a la identificación de señales impulsivas generadas por impactos  Open access

     Molino Minero Re, Erik
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    En este trabajo tesis se estudia el procesado de señales impulsivas generadas por impactos entre cuerpos rígidos. Uno de los problemas que se encuentran al trabajar con impactos es que su análisis generalmente se ve limitado a mediciones indirectas: debido a que las colisiones no se desarrollan directamente sobre el sensor, o bien, porque no es posible instrumentalizar el objeto de colisiona. Esto ocasiona que entre el sensor y el punto de impacto exista un medio de propagación que distorsiona la señal medida. El desarrollo principal de esta tesis se enfoca al problema de cómo compensar o reducir los efectos de dicha distorsión. Para ello, se han investigado y desarrollado los siguientes puntos:1) Estudio de la teoría mecánica del impacto y desarrollo de un modelo matemático del proceso de impacto entre dos cuerpos rígidos. A través de este estudio se investigan las características de las señales impulsivas generadas por colisiones. 2) Definición de una metodología experimental para generar impactos repetibles y determinar los parámetros del modelo matemático. La metodología se sustenta en el diseño e implementación de un prototipo experimental para generar impactos controlados, entre un objeto de prueba y un impactor sensorizado. Para realizar los experimentos se han seleccionado como objetos de prueba un conjunto de cilindros, de aluminio, acero, bronce y latón, en distintos tamaños. Mediante un minucioso estudio y cálculo de los parámetros experimentales, se ha comprobado la validez del modelo matemático. 3) Estudio del problema de la medición indirecta y propuesta de un método de procesado de señales, basado en redes neuronales artificiales, para determinar un filtro inverso que permite estimar la señal del impacto (la fuerza del impacto en función del tiempo). Esta metodología adapta el proceso de entrenamiento a las características de las señales impulsivas que se generan durante una colisión, y que se han identificado a través del estudio y modelado del proceso de impacto. El entrenamiento hace uso de señales reales, que provienen de impactos experimentales generados a distintas velocidades de impacto, y de señales generadas por el modelo matemático. 4) Propuesta de una metodología para estimar el tipo de material y la masa de los objetos de prueba que colisionan. La problemática que se encuentra en este análisis radica en que tanto los objetos como sus respuestas, tienen características similares. Con el método que se propone en este trabajo de tesis, se busca identificar de forma correcta las características de los objetos. El procedimiento considera la extracción de parámetros de las señales vibratorias de los objetos y del uso de redes neuronales para identificar las respuestas.5) Proceso de evaluación experimental de los métodos propuestos. Para determinar la validez de los métodos de procesado antes descrito, primero se analizan los sensores más adecuados para este tipo de señales, que al ser de muy corta duración tienen un ancho de banda muy grande. En segundo lugar, se ha implementado un sistema medición y adquisición para señales impulsivas. Los resultados obtenidos muestran la validez de los métodos propuestos. Con respecto al modelo, se ha verificado su validez con los datos de los distintos objetos de prueba. Asimismo, se ha comprobado que con las señales experimentales, también de los distintos objetos de prueba, el método propuesto para mitigar la distorsión debida a la medición indirecta opera de forma correcta. De la misma forma, el método propuesto para identificar el tipo de material y la masa de los objetos, ha generado resultados satisfactorios.

    In this thesis, the processing of impulsive signals generated by impacts between rigid bodies is investigated. One of the problems found when working with impacts is that their analysis is generally limited to indirect measurements: because collisions do not develop directly on the sensor, or it is not possible to install the sensor on the colliding bodies. This means that between the sensor and the point of impact there is a propagation medium that distorts the measured signal.The main effort of this thesis focuses on the problem of how to compensate or to reduce the effects of such distortion. To do this, the following points have been investigated and developed:1) The study of the mechanical impact theory and the development of a mathematical model of the impact process between two rigid bodies. Through this study, the characteristics of the impulsive signals generated by collisions are investigated.2) Definition of an experimental methodology for generating repeatable impacts and for determining the parameters of the mathematical model. The methodology is based on the design and implementation of an experimental prototype for generating controlled impacts between a test object and a sensorized impactor. To perform the experiments, a set of different test objects have been selected, cylinders made form aluminum, steel, bronze and brass in different sizes. Through a careful study and calculation of the experimental parameters, the validity of the mathematical model has been verified.3) Study of the indirect measurement problem, and proposal of a signal processing method, based on artificial neural networks, to determine an inverse filter in order to estimate the impacting signal (the impact force as a function of the time). This methodology adapts the training process to the characteristics of the impulsive signals that are generated during a collision, and that have been identified through the study and modeling of the impact process. The training uses real signals, which come from experimental impacts generated at different impacting velocities, and signals generated by a mathematical model of the impacting force.4) Proposal for a methodology to estimate the type of material and mass of test objects that collide. The problem found in this analysis is that both, the objects and their responses, have similar characteristics. With the method proposed in this thesis, it is possible to identify correctly the characteristics of one of the objects. The procedure considers the extraction of parameters from the vibrating signals of the objects, and then uses a neural network to classify those parameters.5) Evaluation process of the proposed methods. To determine the validity of the processing methods described above, first, the selection of the most appropriate sensors to acquire these signals has been analyzed (this signals have a very short duration and very large bandwidth). Secondly, a measurement and acquisition system for impulsive signals has been implemented.The experimental results show the validity of the proposed methods. In the case of the model, its validity has been verified with data from different test objects, made from different materials. Also, the proposed method used to deal with the distortion due to the indirect measurement has been tested with experimental data, from impacts with different test objects, and the results show that it operates properly. Likewise, the proposed method to identify the type of material and mass of the test objects has generated satisfactory results.

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    Acceleration of Complex Algorithms on a Fast Reconfigurable Embedded System on Spartan-3  Open access

     Canto Navarro, Enrique Fernando; Fons, Mariano; Lopez Garcia, Mariano; Ramos Lara, Rafael Ramon
    International Conference on Field Programmable Logic and Applications
    p. 429-434
    Presentation's date: 2009-08-31
    Presentation of work at congresses

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    Complex algorithms usually require several computation stages. Many embedded microprocessors have not enough computational performance to resolve these algorithms in a reasonable time, so dedicated coprocessors accelerate them although the main drawback is the area devoted to them. A reconfigurable coprocessor can drastically reduce the area, since it accommodates a set of coprocessors whose execution is multiplexed on time, although the reconfiguration speed reduces the overall system performance. Although self-reconfigurable systems are possible on Spartan-3 FPGAs, it requires a hard design task due to the lack of software and hardware support available on higher-cost families. This paper describes the architecture of a fast self-reconfigurable embedded system mapped on Spartan-3, used as computation platform to solve a complex algorithm, such as the image-processing carried out in a fingerprint biometric algorithm. In order to reduce the reconfiguration time, the system uses our custom-made memory and reconfiguration controllers. Moreover, the dynamic coprocessor can access directly to external memory through our memory controller to improve processing time.

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    Implementación mediante FPGA de un sistema SVM de verificación de locutor  Open access

     Ramos Lara, Rafael Ramon; Lopez Garcia, Mariano; Canto Navarro, Enrique Fernando; Puente Rodriguez, Luis
    Jornadas de Computación Reconfigurable y Aplicaciones
    p. 99-108
    Presentation's date: 2009-09-09
    Presentation of work at congresses

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    Los sistemas biométricos caracterizados por su alto nivel de seguridad se implementan habitualmente con sistemas procesadores de altas prestaciones como los ordenadores personales. Estos procesadores trabajan en un rango de frecuencias de GHz que les permiten realizar millones de operaciones por segundo, de forma que pueden ejecutar en tiempo real complejos algoritmos de verificación. Sin embargo, esta solución de implementación tiene el inconveniente del elevado coste. La utilización de dispositivos programables del tipo FPGA (Field Programmable Gate Array) permite obtener a bajo coste soluciones a medida con las que se consiguen elevadas velocidades de proceso similares a los sistemas μP de altas prestaciones. En este artículo se presenta el diseño e implementación sobre una FPGA de un sistema de verificación de locutor basado en los coeficientes Mel-Cepstrum y en un algoritmo de clasificación SVM (Support Vector Machines). Los resultados experimentales obtenidos con el diseño propuesto muestran una velocidad de proceso equiparable a la conseguida con un ordenador personal basado en el μP Pentium IV.

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    SVM Speaker Verification System Based on a Low-Cost FPGA  Open access

     Ramos Lara, Rafael Ramon; Lopez Garcia, Mariano; Canto Navarro, Enrique Fernando; Puente Rodriguez, Luis
    International Conference on Field Programmable Logic and Applications
    p. 582-586
    Presentation's date: 2009-08-31
    Presentation of work at congresses

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    Biometric systems, characterized by their high confidential levels of security, are usually based on high-performance microprocessors implemented on personal computers. These advanced devices contain floating-point units able to carry out millions of operations per second at frequencies in the GHz range, being qualified to resolve the most complex algorithms in just a few hundred of milliseconds. However, their main drawback is the cost, and the necessary space required to incorporate their external associated peripherals. This disadvantage is especially significant in the low-cost consumer market, where factors such as price and size determine the viability of a product. The use of an FPGA is a suited way to implement systems that require a high computational capability at affordable prices. Besides, these devices allow the design of complex digital systems with outstanding performances in terms of execution times. This paper presents the implementation of a SVM (Support Vector Machines) speaker verification system on a low-cost FPGA. Experimental results show as our system is able to verify a person’s identity as fast as a high-performance microprocessor based on a Pentium IV personal computer.

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    An evaluation of a simple dynamical model for impacts between rigid objects  Open access

     Molino Minero Re, Erik; Lopez Garcia, Mariano; Manuel Lazaro, Antonio; Carlosena Garcia, Alfonso; Roset Juan, Francesc Xavier
    IMEKO World Congress
    p. 2014-2018
    Presentation's date: 2009-09
    Presentation of work at congresses

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    The main purpose of this work is to propose a dynamical model for simulating the response of different metallic objects when impacted by another rigid body. In addition, a methodology for estimating the model parameters is presented and discussed. Results from real experiments shows that by assuming certain characteristics on impacting objects, the dynamic model can reproduce the transient dynamics during contact time.

  • Entorno Didáctico para Sistemas Digitales de Instrumentación y Control

     Ramos Lara, Rafael Ramon; Lopez Garcia, Mariano; Canto Navarro, Enrique Fernando
    Jornadas de Computación Reconfigurable y Aplicaciones
    p. 257-265
    Presentation's date: 2009-09-10
    Presentation of work at congresses

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    En este trabajo se presenta la experiencia didáctica desarrollada por los profesores de la Universidad Politécnica de Cataluña y la Universidad Rovira i Virgili con relación a los dispositivos FPGA (Field Programmable Gate Array) y su actual aplicación tecnológica. En este sentido se expone un conjunto de experiencias prácticas que permiten al estudiante profundizar en el diseño del sistemas de instrumentación y control basados en dispositivos FPGA’s. Las experiencias presentadas forman parte del contenido de la asignatura “Sistemas Digitales de Instrumentación y Control” que se oferta actualmente como asignatura optativa en la Escuela Politécnica Superior de Ingeniería de Vilanova y la Geltrú (UPC).

  • FPGA Implementation of a Minutiae Extraction Fingerprint Algorithm

     Lopez Garcia, Mariano; Enrique, Cantó
    14th International Symposium on Industrial Electronics
    p. 1920-1925
    Presentation of work at congresses

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  • A technique for detecting materials characteristics using mechanical impacts and a multilayer neural network

     Molino Minero Re, Erik; Lopez Garcia, Mariano; Manuel Lazaro, Antonio; Carlosena, A; Shariat, S
    IEEE International Instrumentation and Measurement Technology Conference
    Presentation of work at congresses

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  • Self-Reconfigurable Embedded System on Spartan-3

     Enrique, Cantó; Francesc, Fons; Lopez Garcia, Mariano
    IEEE 18th International Conference on Field Programmable Logic and Applications (FPL'2008)
    p. 571-574
    Presentation of work at congresses

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  • Self-Reconfiguration of Embedded Systems Mapped on Spartan-3

     Enrique, Cantó; Lopez Garcia, Mariano; Francesc, Fons
    Reconfigurable Communication-centric Systems-on-Chip workshop 2008 - ReCoSoC'08
    p. 117-123
    Presentation of work at congresses

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  • Evaluation of impacting signals and neural networks for objects detection

     Molino Minero Re, Erik; Lopez Garcia, Mariano; Manuel Lazaro, Antonio
    14th International Symposium on Industrial Electronics
    p. 925-928
    Presentation of work at congresses

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  • Procesador de alineamiento de huella dactilar

     Fons, M; Fons, F; Canto, E Y Lopez M; Lopez Garcia, Mariano
    II Congreso Español de Informática. VII Jornadas de Computación Reconfigurable y Aplicaciones (JCRA'07)
    Presentation of work at congresses

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  • Procesador hardware auto-reconfigurable de huella dactilar

     Fons, F; Fons, M; Canto, E Y Lopez M; Lopez Garcia, Mariano
    II Congreso Español de Informática. VII Jornadas de Computación Reconfigurable y Aplicaciones (JCRA'07)
    Presentation of work at congresses

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  • Flexible hardware for fingerprint image processng

     Fons, F; Fons, M; Canto, E Y Lopez M; Lopez Garcia, Mariano
    II Congreso Español de Informática. VII Jornadas de Computación Reconfigurable y Aplicaciones (JCRA'07)
    Presentation of work at congresses

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  • Flexible hardware for fingerprint image processing

     Fons Lluis, Francesc; Fons LLuis, Mariano; Cantó Navarro, Enrique; Lopez Garcia, Mariano
    Conference on Ph.D. Research in Microelectronics and Electronics
    p. 169-172
    DOI: 10.1109/RME.2007.4401839
    Presentation's date: 2007-05-02
    Presentation of work at congresses

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    Reconfigurable computing adds to the traditional hardware/software design flow a new degree of freedom in the development of electronic systems. In a system-on-chip platform, the fact that a MCU makes evolve at run-time a hardware coprocessor mapped on a FPGA, to execute thus different compute-intensive tasks in the same silicon-area, results in a clear earned value applied to the system implementation: the low-cost reached through the resources time-multiplexing. Under that approach, this work merges both reconfigurable computing and HW/SW co-design technologies to develop an efficient architecture of an automatic fingerprint authentication system (AFAS) oriented to real-time embedded applications.

  • Dynamically Reconfigure CORDIC Coprocessor for Trigonometric Computing

     Francesc, Fons; Enrique, Cantó; Lopez Garcia, Mariano
    19th International Conference on Architecture of Computing Systems ARCS'06
    p. 254-263
    Presentation of work at congresses

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  • PIBES: Desarrollo de Coprocesadores Biométricos en Hardware Autoreconfigurable (TEC2006-12365-C02-02)

     Lopez Garcia, Mariano; Ramos Lara, Rafael Ramon; Del Rio Fernandez, Joaquin; Cantó, Enrique
    Competitive project

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  • Automatic design flow for multi-contest FPGAs

     Cantó, E; Lopez Garcia, Mariano; Fons, F; Del Rio Fernandez, Joaquin; Manuel Lazaro, Antonio
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation of work at congresses

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  • Hardware coprocessor design for fingerprint image enhancement

     Lopez Garcia, Mariano; Cantó, E; Fons, M; Manuel Lazaro, Antonio; Del Rio Fernandez, Joaquin
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation of work at congresses

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  • Hardware-Software co-design of a fingerprint matcher on card

     Francesc, Fons; Enrique, Cantó; Lopez Garcia, Mariano
    2006 IEEE Internatinal Conference on Electro/Information Technology
    Presentation of work at congresses

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  • Inverse filtering approximation for impacting signals estimation using a multilayer neural network

     Molino Minero Re, Erik; Lopez Garcia, Mariano; Del Rio Fernandez, Joaquin; Manuel Lazaro, Antonio
    Annual Conference of the IEEE Industrial Electronics Society
    Presentation of work at congresses

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  • FPGA implementation of a ridge extraction fingerprint algorithm based on croblaze and gradware coprocessor

     Enrique, Cantó; Lopez Garcia, Mariano
    16th international conference on Field Programmable Logic and Applications
    Presentation of work at congresses

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  • Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip

     Francesc, Fons; Enrique, Cantó; Lopez Garcia, Mariano
    II International Workshop on Applied Reconfigurable CORDIC System-on-Chip
    p. 122-127
    Presentation of work at congresses

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  • Hardware-Software Co-design of a Fingerprint Image Enhancement Algorithm

     Enrique, Cantó; Lopez Garcia, Mariano; Francesc, Fons
    The 32nd Annual Conference of the IEEE Industrial Electronic Society
    Presentation of work at congresses

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  • Reconfigurable OPB Coprocessor for a Microblaze Self-Reconfigurable SOC Mapped on Spartan-3 FPGAs

     Enrique, Cantó; Lopez Garcia, Mariano; Francesc, Fons
    The 32nd Annual Conference of the IEEE Industrial Electronic Society
    Presentation of work at congresses

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  • Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip

     Francesc, Fons; Enrique, Cantó; Lopez Garcia, Mariano
    Lecture notes in computer science
    Vol. 3546, p. 122-127
    Date of publication: 2006-03
    Journal article

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  • Deconvolution of impulsive signals with adaptative filters

     Molino Minero Re, Erik; Lopez Garcia, Mariano; Del Rio Fernandez, Joaquin; Manuel Lazaro, Antonio
    International Workshop on Marine Technology
    Presentation of work at congresses

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  • Coprocesador para la esqueletización de huellas dactilares

     Enrique, Cantó; Lopez Garcia, Mariano; Canyelles, Nicolau; Palomera, M; Francesc, Fons I Mariano Fons
    V JORNADAS COMPUTACION RECONFIGURABLE Y APLICACIONES 2005
    p. 103-108
    Presentation of work at congresses

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  • Hardware-Software Co-design of an Automatic Fingerprint Acquisition System

     Francesc, Fons; Canyellas, Nicolau; Enrique, Cantó; Lopez Garcia, Mariano
    IEEE International Symposium on Industrial Electronics
    p. 1123-1128
    Presentation of work at congresses

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  • Design flow for DSP&FPGA algorithms with Matlab

     Del Rio Fernandez, Joaquin; Lopez Garcia, Mariano; Manuel Lazaro, Antonio; Molino Minero Re, Erik; Carlosena, A
    International Workshop on Marine Technology
    Presentation of work at congresses

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  • Hardware-Software Codesign of a Fingerprint Identification Algorithm

     Canyellas, Nicolau; Enrique, Cantó; Giuseppe, Forte; Lopez Garcia, Mariano
    5th. Audio- and Video-based Biometric Person Authentication
    p. 683-692
    Presentation of work at congresses

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  • Hardware-software co-design for fingerprint biomedic identification

     Lopez Garcia, Mariano
    Instrumentation viewpoint
    Vol. 3, p. 7-10
    Date of publication: 2005-04
    Journal article

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  • Deconvolution of impusive signals with adaptative filters

     Molino Minero Re, Erik; Lopez Garcia, Mariano; Del Rio Fernandez, Joaquin; Manuel Lazaro, Antonio
    Instrumentation viewpoint
    num. 4, p. 38-39
    Date of publication: 2005-11
    Journal article

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  • Design flow for DSP&FPGA algorithms with matlab

     Del Rio Fernandez, Joaquin; Lopez Garcia, Mariano; Manuel Lazaro, Antonio; Molino Minero Re, Erik; Carlosena, A
    Instrumentation viewpoint
    num. 4, p. 77-79
    Date of publication: 2005-11
    Journal article

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  • Hardware-software codesign of a fingerprint identification algorithm

     Lopez Garcia, Mariano
    Lecture notes in computer science
    Vol. 3546, p. 683-692
    Date of publication: 2005-01
    Journal article

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  • DELFIN - DESARROLLO DE UN SISTEMA DE CO-PROCESAMIENTO DE HUELLAS DACTILARES

     Lopez Garcia, Mariano; Deschamps, J.P.
    Competitive project

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