Canal Corretger, Ramon
Total activity: 125
Areas of expertise
DRAM, Memory Design, Microarchitecture, Nanotechnology Circuit Design, Near and Subthreshold Architectures, Non-Volatile Memories, Processor Design, SRAM, Variability
h index
14
Professional category
University lecturer
Doctoral courses
Doctor per la Universitat Politècnica de Catalunya
University degree
Enginyer en Informàtica
Research group
ARCO - Microarchitecture and Compilers
Department
Department of Computer Architecture
School
Barcelona School of Informatics (FIB)
E-mail
rcanalac.upc.edu
Contact details
UPC directory Open in new window
Orcid
0000-0003-4542-204X Open in new window
ResearcherID
E-7775-2014 Open in new window
Scopus Author ID
7004495853 Open in new window
Links of interest
Personal webpage Open in new window

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1 to 50 of 125 results
  • Cross-layer early reliability evaluation: Challenges and promises

     Di Carlo, Stefano; Vallero, Alessandro; Gizopoulos, Dimitris; Di Natale, Giorgio; Gonzalez Colas, Antonio Maria; Canal Corretger, Ramon; Mariani, Riccardo; Pipponzi, Mauro; Grasset, Arnaud; Bonnot, Philippe; Reichenbach, Frank; Rafiq, Gulzaib; Loekstad, Trond
    IEEE International On-Line Testing Symposium
    p. 228-233
    DOI: 10.1109/IOLTS.2014.6873704
    Presentation's date: 2014-07-07
    Presentation of work at congresses

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    Evaluation of computing systems reliability must be accurate enough to provide hints for the required fault protection mechanisms that will guarantee correctness of operation at acceptance costs. To be useful, reliability evaluation must be performed early enough in the design cycle when, however, the available details of the system are largely unknown. This inherent contradiction in terms: early vs. accurate, requires a cross-layer approach for reliability evaluation. Different layers of abstraction contribute differently in the overall system reliability; if this contribution can be assessed independently, the reliability of the system can be evaluated at the early stages of the design. We review the state-of-the-art in the area and discuss corresponding challenges.

  • Reliability In The Face of Variability in Nanometer Embedded Memories  Open access

     Ganapathy, Shrikanth
    Universitat Politècnica de Catalunya
    Theses

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    En esta tesis, se ha investigado el impacto de las variaciones paramétricas en el comportamiento de una estructura de procesador rendimiento crítico - recuerdos incrustados. Como variaciones se manifiestan como una distribución del consumo y el rendimiento, como primer paso , se propone una nueva metodología de modelado que ayuda a evaluar el impacto de las optimizaciones a nivel de circuito en las opciones de diseño a nivel de arquitectura. Después complementamos estas optimizaciones en tiempo de diseño con un mecanismo en tiempo de ejecución basado en body-biasing. Nuestra propuesta utiliza una novedosa variante totalmente digital de seguimiento de hardware mediante incrustado DRAM células (EDRAM) para monitorear los cambios en tiempo de ejecución de la latencia de la memoria caché. Un generador de biasing utiliza estas mediciones para generar el voltaje de polarización óptimo para cumplir con los objetivos de rendimiento requeridos.Además de lo anterior, esta tesis propone una nueva celda de memoria eDRAM que tolera mejor las variaciones y los impactos de particulas. Esta celda es una alternativa a los diseños actuales basados ??en SRAM. En el dominio de ultra bajo consumo de energía cuando la operación segura está limitada por la tensión mínima de funcionamiento (Vddmin), se analiza el impacto de las fallas en los márgenes funcionales. Con este fin, hemos desarrollado una herramienta totalmente automatizada (INFORMER) capaz de calcular mediciones de toda la memoria, como la energía , el rendimiento y yield con precisión y rapidez. Usando la herramienta desarrollada, evaluamos la efectividad de una nueva clase de técnicas híbridas en la mejora de yield de la memoria caché mediante la prevención y corrección de fallas. Tener una perspectiva holística de las métricas de rendimiento de toda la memoria nos ayuda a llegar a diseños optimizados necesarios para el correcto funcionamiento durante toda la vida útil de la memoria.

    In this thesis, we have investigated the impact of parametric variations on the behaviour of one performance-critical processor structure - embedded memories. As variations manifest as a spread in power and performance, as a first step, we propose a novel modeling methodology that helps evaluate the impact of circuit-level optimizations on architecture-level design choices. Choices made at the design-stage ensure conflicting requirements from higher-levels are decoupled. We then complement such design-time optimizations with a runtime mechanism that takes advantage of adaptive body-biasing to lower power whilst improving performance in the presence of variability. Our proposal uses a novel fully-digital variation tracking hardware using embedded DRAM (eDRAM) cells to monitor run-time changes in cache latency and leakage. A special fine-grain body-bias generator uses the measurements to generate an optimal body-bias that is needed to meet the required yield targets. A novel variation-tolerant and soft-error hardened eDRAM cell is also proposed as an alternate candidate for replacing existing SRAM-based designs in latency critical memory structures. In the ultra low-power domain where reliable operation is limited by the minimum voltage of operation (Vddmin), we analyse the impact of failures on cache functional margin and functional yield. Towards this end, we have developed a fully automated tool (INFORMER) capable of estimating memory-wide metrics such as power, performance and yield accurately and rapidly. Using the developed tool, we then evaluate the #effectiveness of a new class of hybrid techniques in improving cache yield through failure prevention and correction. Having a holistic perspective of memory-wide metrics helps us arrive at design-choices optimized simultaneously for multiple metrics needed for maintaining lifetime requirements.

  • DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy

     Jaksic, Zoran; Canal Corretger, Ramon
    Design, Automation and Test in Europe
    DOI: 10.7873/DATE2014.094
    Presentation's date: 2014-03
    Presentation of work at congresses

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    Recent technology trends has turned DRAMs into an interesting candidate to substitute traditional SRAM-based on-chip memory structures (i.e. register file, cache memories). Nevertheless, a major problem to introduce these cells is that they lose their state (i.e. value) over time, and they have to be refreshed. This paper proposes the implementation of coherent caches with DRAM cells. Furthermore, we propose to use the coherence state to tune the refresh overhead. According to our analysis, an average of up to 57% of refresh energy can be saved. Also, comparing to the caches implemented in SRAMs total energy savings are on average up to 39% depending of the refresh policy with a performance loss below 8%.

  • INFORMER: an integrated framework for early-stage memory robustness analysis

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Eric; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    Design, Automation and Test in Europe
    p. 1-4
    DOI: 10.7873/DATE2014.046
    Presentation's date: 2014-03-24
    Presentation of work at congresses

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    With the growing importance of parametric (process and environmental) variations in advanced technologies, it has become a serious challenge to design reliable, fast and low-power embedded memories. Adopting a variation-aware design paradigm requires a holistic perspective of memory-wide metrics such as yield, power and performance. However, accurate estimation of such metrics is largely dependent on circuit implementation styles, technology parameters and architecture-level specifics. In this paper, we propose a fully automated tool - INFORMER - that helps high-level designers estimate memory reliability metrics rapidly and accurately. The tool relies on accurate circuit-level simulations of failure mechanisms such as soft-errors and parametric failures. The statistics obtained can then help couple low-level metrics with higher-level design choices. A new technique for rapid estimation of low-probability failure events is also proposed. We present three use-cases of our prototype tool to demonstrate its diverse capabilities in autonomously guiding large SRAM based robust memory designs. © 2014 EDAA.

  • SSFB: a highly-efficient and scalable simulation reduction technique for SRAM yield analysis

     Rana, Manish; Canal Corretger, Ramon
    Design, Automation and Test in Europe
    p. 1-6
    DOI: 10.7873/DATE2014.045
    Presentation's date: 2014-03-24
    Presentation of work at congresses

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    Estimating extremely low SRAM failure-probabilities by conventional Monte Carlo (MC) approach requires hundreds-of-thousands simulations making it an impractical approach. To alleviate this problem, failure-probability estimation methods with a smaller number of simulations have recently been proposed, most notably variants of consecutive mean-shift based Importance Sampling (IS). In this method, a large amount of time is spent simulating data points that will eventually be discarded in favor of other data-points with minimum norm. This can potentially increase the simulation time by orders of magnitude. To solve this very important limitation, in this paper, we introduce SSFB: A novel SRAM failure-probability estimation method that has much better cognizance of the data points compared to conventional approaches. The proposed method starts with radial simulation of a single point and reduces discarded simulations by: a) random sampling-only-when it reaches a failure boundary and after that continues again with radial simulation of a chosen point, and b) random sampling is performed-only-within a specific failure-range which decreases in each iteration. The proposed method is also scalable to higher dimensions (more input variables) as sampling is done on the surface of the hyper-sphere, rather than within-the-hypersphere as other techniques do. Our results show that using our method we can achieve an overall 40x reduction in simulations compared to consecutive mean-shift IS methods while remaining within the 0.01-Sigma accuracy. © 2014 EDAA.

  • Microarquitectura y Compiladores para Futuros Procesadores III

     Gonzalez Colas, Antonio Maria; Parcerisa Bundó, Joan Manuel; Canal Corretger, Ramon; Cruz Diaz, Josep-llorenç; Bosque Arbiol, Ana; Zyulkyarov, Ferad; Sanchez Pedreño, Daniel; Molina Clemente, Carlos Maria; Aliagas Castell, Carles; García Guirado, Antonio; Tubella Murgadas, Jordi
    Competitive project

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  • Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells

     Amat Bertran, Esteve; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio; Canal Corretger, Ramon
    IEEE International Midwest Symposium on Circuits and Systems
    p. 81-84
    DOI: 10.1109/MWSCAS.2013.6674590
    Presentation's date: 2013-08-05
    Presentation of work at congresses

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    3T1D-DRAM cells will still be operative with 7nm FinFETs but their performance is significantly degraded when factoring in variability. In order to improve the cell robustness against device process variation and high environment temperatures, we propose a Dual-VT strategy. Our results show a larger retention time, significant cell spread reduction and reliable behavior up to 100°C.

  • An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

     Jing, Naifeng; Shen, Yao; Lu, Yao; Ganapathy, Shrikanth; Mao, Zhigang; Guo, Minyi; Canal Corretger, Ramon; Liang, Xiaoyao
    Annual International Symposium on Computer Architecture
    p. 344-355
    DOI: 10.1145/2485922.2485952
    Presentation's date: 2013-06
    Presentation of work at congresses

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    The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for traditional SRAM designs in the future technologies. In this paper, we propose to use embedded-DRAM (eDRAM) as an alternative in future GPGPUs. Compared with SRAM, eDRAM provides higher density and lower leakage power. However, the limited data retention time in eDRAM poses new challenges. Periodic refresh operations are needed to maintain data integrity. This is exacerbated with the scaling of eDRAM density, process variations and temperature. Unlike conventional CPUs which make use of multi-ported RF, most of the RFs in modern GPGPU are heavily banked but not multi-ported to reduce the hardware cost. This provides a unique opportunity to hide the refresh overhead. We propose two different eDRAM implementations based on 3T1D and 1T1C memory cells. To mitigate the impact of periodic refresh, we propose two novel refresh solutions using bank bubble and bank walk-through. Plus, for the 1T1C RF, we design an interleaved bank organization together with an intelligent warp scheduling strategy to reduce the impact of the destructive reads. The analysis shows that our schemes present better energy efficiency, scalability and variation tolerance than traditional SRAM-based designs.

  • Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes

     Lorente, Vicente; Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Canal Corretger, Ramon; López, Pedro; Duato, José
    Design, Automation and Test in Europe
    p. 83-88
    DOI: 10.7873/DATE.2013.031
    Presentation's date: 2013-03-20
    Presentation of work at congresses

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    Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors at supply voltages below Vccmin.

    Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors at supply voltages below Vccmin. Recent proposals provide a rather low fault-coverage due to the fault coverage/overhead trade-off. We propose a new fault- tolerant L1 cache, which combines SRAM and eDRAM cells in L1 data caches to provide 100% SRAM hard-error fault coverage. Results show that, compared to a conventional cache and assuming 50% failure probability at low-power mode, leakage and dynamic energy savings are by 85% and 62%, respectively, with a minimal impact on performance.

  • Effectiveness of hybrid recovery techniques on parametric failures

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    International Symposium on Quality Electronic Design
    p. 258-264
    DOI: 10.1109/ISQED.2013.6523620
    Presentation's date: 2013-03
    Presentation of work at congresses

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    Modern day microprocessors effectively utilise supply voltage scaling for tremendous power reduction. The minimum voltage beyond which a processor cannot operate reliably is defined as V ddmin. On-chip memories like caches are the most susceptible to voltage-noise induced failures because of process variations and reduced noise-margins thereby arbitrating whole processor's V ddmin. In this paper, we evaluate the effectiveness of a new class of hybrid techniques in improving cache yield through failure prevention and correction. Proactive read/write assist techniques like body-biasing (BB) and wordline boosting (WLB) when combined with reactive techniques like ECC and redundancy are shown to offer better quality-energy-area trade offs when compared to their standalone configurations. Proactive techniques can help lower V ddmin (improving functional margin) for significant power savings and reactive techniques ensure that the resulting large number of failures are corrected (improving functional yield). Our results in 22nm technology indicate that at scaled supply voltages, hybrid techniques can improve parametric yield by atleast 28% when considering worst-case process variations

  • Impact of bulk/SOI 10nm FinFETs on 3T1D-DRAM cell performance

     Amat Bertran, Esteve; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    International Conference on Solid-State and Integrated Circuit Technology
    p. 1-3
    DOI: 10.1109/ICSICT.2012.6466713
    Presentation's date: 2012-10
    Presentation of work at congresses

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    While the feasibility of SOI or bulk substrates for 10nm FinFETs has been shown, their impact on 3T1D memory performance has not been studied yet. In our study, bulk-based FinFETs show a better behavior for golden devices. Nevertheless, when variation is factored in, SOI-based FinFETs present better tolerance and, consequently, lower performance spread than bulk-based devices. When considering environment temperature it is always a detrimental factor for both multi-gate devices, but the impact is lower for the bulk ones.

  • Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs

     Jaksic, Zoran; Canal Corretger, Ramon
    IEEE International Conference on Computer Design: VLSI in Computers and Processors
    p. 309-314
    DOI: 10.1109/ICCD.2012.6378657
    Presentation's date: 2012-10-02
    Presentation of work at congresses

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    In this paper, we present the dynamic 3T memory cell for future 10 nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access time, retention time, and static power consumption of the cell when it is exposed to the effects of process and environmental variations. Process variations are extracted from the ITRS predictions and they are modeled at device level. For simulation, we use 10 nm SOI tri-gate FinFET BSIM-CMG model card developed by the University of Glasgow, Device Modeling Group. When compared to the classical 6T SRAM, 3T cell has 40% smaller area, leakage is reduced up to 14 times while access time is approximately the same. In order to achieve higher retention times,we propose several cell extensions which, at the same time, enable post-fabrication/run-time adaptability.

    In this paper, we pr esent the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access time, retention time, and static power consumption of the cell when it is exposed to the effects of process and environmental variations. Process variations are extracted from the ITRS predictions and they are modeled at device level. For simulation, we use 10nm SOI tri-gate FinFET BSIM-CMG model card developed by the University of Glasgow, Device Modeling Group. When compared to the classical 6T SRAM, 3T cell has 40% smaller area, leakage is reduced up to 14 times while access time is approximately the same. In order to achieve higher retention times, we propose several cell extensions which, at the same time, enable post- fabrication/run-time adaptability.

  • A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Eric; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    IEEE International Conference on Computer Design: VLSI in Computers and Processors
    p. 472-477
    DOI: 10.1109/ICCD.2012.6378681
    Presentation's date: 2012-10-02
    Presentation of work at congresses

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    In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment.

    In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment

  • A Novel variation-tolerant 4T-DRAM with enhance soft-error tolerance

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    IEEE International Conference on Computer Design: VLSI in Computers and Processors
    p. 472-477
    DOI: 10.1109/ICCD.2012.6378681
    Presentation's date: 2012-09-30
    Presentation of work at congresses

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    In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment.

  • Analysis of FinFET technology on memories

     Amat, E.; ASenov, Asen; Canal Corretger, Ramon; Cheng, B.; Cruz Diaz, Josep-llorenç; Jaksic, Zoran; Miranda, Miguel; Rubio Sola, Jose Antonio; Zuber, Paul
    IEEE International On-Line Testing Symposium
    p. 169
    DOI: 10.1109/IOLTS.2012.6313866
    Presentation's date: 2012-06-29
    Presentation of work at congresses

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  • IEEE On-Line Testing Symposium 2012

     Cruz Diaz, Josep-llorenç; Ganapathy, Shrikanth; Jaksic, Zoran; Canal Corretger, Ramon
    Competitive project

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  • Enhancing 6T SRAM cell stabilitty by back gate biasing techniques for 10nm SOI FinFETs under process and environmental variations

     Jaksic, Zoran; Canal Corretger, Ramon
    International Conference Mixed Design of Integrated Circuits and Systems
    p. 103-108
    Presentation's date: 2012-05-26
    Presentation of work at congresses

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  • Strain relevance on the improvement of the 3T1D cell performance

     Amat Bertran, Esteve; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    International Conference Mixed Design of Integrated Circuits and Systems
    p. 120-123
    Presentation's date: 2012-05-26
    Presentation of work at congresses

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  • Process variability in sub-16nm bulk CMOS technology

     Rubio Sola, Jose Antonio; Figueras Pamies, Juan; Vatajelu, Elena Ioana; Canal Corretger, Ramon
    Date: 2012-03-01
    Report

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  • Access to the full text
    Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm  Open access  awarded activity

     Amat Bertran, Esteve; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    Conference on Design of Circuits and Integrated Systems
    p. 1-5
    Presentation's date: 2012
    Presentation of work at congresses

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    3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that the variability of the write access transistor has turn into the more detrimental device for the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some strategies to mitigate the cell variability.

    3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that the variability of the write access transistor has turn into the more detrimental device for the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some strategies to mitigate the cell variability.

  • On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    Date: 2011-12-05
    Report

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    In this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive techniques like ECC and redundancy which cope with already existent failures. While proactive and reactive have been previously viewed as complementary techniques, we show that it is not necessarily the case when considering the benefits of such hybrid schemes.

    Postprint (author’s final draft)

  • Adaptive Memory Hierarchies For Next Generation Tiled Microarchitectures  Open access  awarded activity

     Herrero Abellanas, Enric
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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    Les últimes dècades el rendiment dels processadors i de les memòries ha millorat a diferent ritme, limitant el rendiment dels processadors i creant el conegut memory gap. Sol·lucionar aquesta diferència de rendiment és un camp d'investigació d'actualitat i que requereix de noves sol·lucions. Una sol·lució a aquest problema són les memòries “cache”, que permeten reduïr l'impacte d'unes latències de memòria creixents i que conformen la jerarquia de memòria. La majoria de d'organitzacions de les “caches” estan dissenyades per a uniprocessadors o multiprcessadors tradicionals. Avui en dia, però, el creixent nombre de transistors disponible per xip ha permès l'aparició de xips multiprocessador (CMPs). Aquests xips tenen diferents propietats i limitacions i per tant requereixen de jerarquies de memòria específiques per tal de gestionar eficientment els recursos disponibles. En aquesta tesi ens hem centrat en millorar el rendiment i la eficiència energètica de la jerarquia de memòria per CMPs, des de les “caches” fins als controladors de memòria. A la primera part d'aquesta tesi, s'han estudiat organitzacions tradicionals per les “caches” com les privades o compartides i s'ha pogut constatar que, tot i que funcionen bé per a algunes aplicacions, un sistema que s'ajustés dinàmicament seria més eficient. Tècniques com el Cooperative Caching (CC) combinen els avantatges de les dues tècniques però requereixen un mecanisme centralitzat de coherència que té un consum energètic molt elevat. És per això que en aquesta tesi es proposa el Distributed Cooperative Caching (DCC), un mecanisme que proporciona coherència en CMPs i aplica el concepte del cooperative caching de forma distribuïda. Mitjançant l'ús de directoris distribuïts s'obté una sol·lució més escalable i que, a més, disposa d'un mecanisme de marcatge més flexible i eficient energèticament. A la segona part, es demostra que les aplicacions fan diferents usos de la “cache” i que si es realitza una distribució de recursos eficient es poden aprofitar els que estan infrautilitzats. Es proposa l'Elastic Cooperative Caching (ElasticCC), una organització capaç de redistribuïr la memòria “cache” dinàmicament segons els requeriments de cada aplicació. Una de les contribucions més importants d'aquesta tècnica és que la reconfiguració es decideix completament a través del maquinari i que tots els mecanismes utilitzats es basen en estructures distribuïdes, permetent una millor escalabilitat. ElasticCC no només és capaç de reparticionar les “caches” segons els requeriments de cada aplicació, sinó que, a més a més, és capaç d'adaptar-se a les diferents fases d'execució de cada una d'elles. La nostra avaluació també demostra que la reconfiguració dinàmica de l'ElasticCC és tant eficient que gairebé proporciona la mateixa taxa de fallades que una configuració amb el doble de memòria.Finalment, la tesi es centra en l'estudi del comportament de les memòries DRAM i els seus controladors en els CMPs. Es demostra que, tot i que els controladors tradicionals funcionen eficientment per uniprocessadors, en CMPs els diferents patrons d'accés obliguen a repensar com estan dissenyats aquests sistemes. S'han presentat múltiples sol·lucions per CMPs però totes elles es veuen limitades per un compromís entre el rendiment global i l'equitat en l'assignació de recursos. En aquesta tesi es proposen els Thread Row Buffers (TRBs), una zona d'emmagatenament extra a les memòries DRAM que permetria guardar files de dades específiques per a cada aplicació. Aquest mecanisme permet proporcionar un accés equitatiu a la memòria sense perjudicar el seu rendiment global. En resum, en aquesta tesi es presenten noves organitzacions per la jerarquia de memòria dels CMPs centrades en la escalabilitat i adaptativitat als requeriments de les aplicacions. Els resultats presentats demostren que les tècniques proposades proporcionen un millor rendiment i eficiència energètica que les millors tècniques existents fins a l'actualitat.

    Processor performance and memory performance have improved at different rates during the last decades, limiting processor performance and creating the well known "memory gap". Solving this performance difference is an important research field and new solutions must be proposed in order to have better processors in the future. Several solutions exist, such as caches, that reduce the impact of longer memory accesses and conform the system memory hierarchy. However, most of the existing memory hierarchy organizations were designed for single processors or traditional multiprocessors. Nowadays, the increasing number of available transistors has allowed the apparition of chip multiprocessors, which have different constraints and require new ad-hoc memory systems able to efficiently manage memory resources. Therefore, in this thesis we have focused on improving the performance and energy efficiency of the memory hierarchy of chip multiprocessors, ranging from caches to DRAM memories. In the first part of this thesis we have studied traditional cache organizations such as shared or private caches and we have seen that they behave well only for some applications and that an adaptive system would be desirable. State-of-the-art techniques such as Cooperative Caching (CC) take advantage of the benefits of both worlds. This technique, however, requires the usage of a centralized coherence structure and has a high energy consumption. Therefore we propose the Distributed Cooperative Caching (DCC), a mechanism to provide coherence to chip multiprocessors and apply the concept of cooperative caching in a distributed way. Through the usage of distributed directories we obtain a more scalable solution and, in addition, has a more flexible and energy-efficient tag allocation method. We also show that applications make different uses of cache and that an efficient allocation can take advantage of unused resources. We propose Elastic Cooperative Caching (ElasticCC), an adaptive cache organization able to redistribute cache resources dynamically depending on application requirements. One of the most important contributions of this technique is that adaptivity is fully managed by hardware and that all repartitioning mechanisms are based on distributed structures, allowing a better scalability. ElasticCC not only is able to repartition cache sizes to application requirements, but also is able to dynamically adapt to the different execution phases of each thread. Our experimental evaluation also has shown that the cache partitioning provided by ElasticCC is efficient and is almost able to match the off-chip miss rate of a configuration that doubles the cache space. Finally, we focus in the behavior of DRAM memories and memory controllers in chip multiprocessors. Although traditional memory schedulers work well for uniprocessors, we show that new access patterns advocate for a redesign of some parts of DRAM memories. Several organizations exist for multiprocessor DRAM schedulers, however, all of them must trade-off between memory throughput and fairness. We propose Thread Row Buffers, an extended storage area in DRAM memories able to store a data row for each thread. This mechanism enables a fair memory access scheduling without hurting memory throughput. Overall, in this thesis we present new organizations for the memory hierarchy of chip multiprocessors which focus on the scalability and of the proposed structures and adaptivity to application behavior. Results show that the presented techniques provide a better performance and energy-efficiency than existing state-of-the-art solutions.

  • Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells

     Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria
    ACM Great Lakes Symposium on VLSI
    p. 227-282
    DOI: 10.1145/1973009.1973065
    Presentation's date: 2011-05-18
    Presentation of work at congresses

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    Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure could exhibit serious limitations in future CMOS technologies due to the instability caused by transistor mismatching as well as for leakage consumption reasons. For L1 data caches the new cell 3T1D DRAM is considered a potential candidate to substitute 6T SRAMs. We first evaluate the impact of the positive bias temperature instability, PBTI, on the access and retention time of the 3T1D memory cell implemented with 45 nm technology. Then, we consider all sources of variations and the effect of the degradation caused by the aging of the device on the yield at system level.

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    Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors  Open access

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    Date: 2011-04-15
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    In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations.

  • MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES II

     Parcerisa Bundó, Joan Manuel; Canal Corretger, Ramon; Tubella Murgadas, Jordi; Cruz Diaz, Josep-llorenç; Gonzalez Colas, Antonio Maria
    Competitive project

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  • TRAMS Project: variability and reliability of SRAM memories in sub-22 nm Bulk-CMOS technologies

     Canal Corretger, Ramon; Rubio Sola, Jose Antonio; ASenov, Asen; Brown, A.; Miranda, Miguel; Zuber, Paul; Gonzalez Colas, Antonio Maria; Vera, Xavier
    European Future Technologies Conference and Exhibition
    p. 148-149
    DOI: 10.1016/j.procs.2011.09.010
    Presentation's date: 2011
    Presentation of work at congresses

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  • New reliability mechanisms in memory design for sub-22nm technologies

     Aymerich Capdevila, Nivard; Brown, A.; Canal Corretger, Ramon; Cheng, B.; Figueras Pamies, Juan; Gonzalez Colas, Antonio Maria; Herrero Abellanas, Enric; Markov, S.; Miranda, Miguel; Pouyan, Peyman; Ramirez Garcia, Tanausu; Rubio Sola, Jose Antonio; Vatajelu, I.; Vera, Xavier; Wang, W.; Zuber, Paul; ASenov, Asen
    IEEE International On-Line Testing Symposium
    p. 111-114
    DOI: 10.1109/IOLTS.2011.5993820
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  • Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    IEEE International Conference on Computer Design: VLSI in Computers and Processors
    p. 332-338
    DOI: 10.1109/ICCD.2011.6081420
    Presentation's date: 2011
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  • Cooperative caching for clip multiprocessors

     Chang, J. Chang; Herrero Abellanas, Enric; Canal Corretger, Ramon; Sohi, G.
    Date of publication: 2011
    Book chapter

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    vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells  Open access

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    Date: 2010-09-05
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    In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is composed of a discretization hardware that exploits the delay/leakage dependence on variability sources characteristic for categorization

  • Power-efficient spilling techniques for chip multiprocessors

     Herrero Abellanas, Enric; González, José; Canal Corretger, Ramon
    International European Conference on Parallel and Distributed Computing
    p. 256-267
    DOI: 10.1007/978-3-642-15277-1_25
    Presentation's date: 2010-09-02
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    Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the latency and high-demand of the on-chip network and the off-chip memory communication. To optimize the usage of on-chip memory space and reduce off-chip traffic several techniques have proposed to use the N-chance forwarding mechanism, a solution for distributing unused cache space in chip multiprocessors. This technique, however, can lead in some cases to extra unnecessary network traffic or inefficient cache allocation. This paper presents two alternative power-efficient spilling methods to improve the efficiency of the N-chance forwarding mechanism. Compared to traditional Spilling, our Distance-Aware Spilling technique provides an energy efficiency improvement (MIPS3/W) of 16% on average, and a reduction of the network usage of 14% in a ring configuration while increasing performance 6%. Our Selective Spilling technique is able to avoid most of the unnecessary reallocations and it doubles the reuse of spilled blocks, reducing network traffic by an average of 22%. A combination of both techniques allows to reduce the network usage by 30% on average without degrading performance, allowing a 9% increase of the energy efficiency.

  • MODEST: a model for energy estimation under spatio-temporal variability

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    International Symposium on Low Power Electronics and Design
    p. 129-134
    Presentation's date: 2010-08-20
    Presentation of work at congresses

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    Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental conditions which makes the problem of energy estimation more dynamic in nature. It is worsened by process induced variations of low level parameters like threshold voltage and channel length. In this paper we present MODEST, a proposal for estimating the static and dynamic energy of caches taking into account spatial variations of physical parameters, temporal changes of supply voltage and environmental factors like temperature. It can be used to estimate the energy of different blocks of a cache based on a combination empirical data and analytical equations. The observed maximum and median error between MODEST and HSPICE energy-estimates for 22,500 samples is around 7.8% and 0.5% respectively. As a case study, using MODEST, we propose a two step iterative optimization procedure involving Dual-Vth assignment and standby supply voltage minimization for reclaiming energy-constrained caches. The observed energy reduction is around 50.8% for the most-leaky Cache. A speed-up of 750X over conventional hard-coded implementation for such optimizations is achieved.

  • Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors

     Herrero Abellanas, Enric; González, José; Canal Corretger, Ramon
    International Symposium on Computer Architecture
    p. 419-428
    Presentation's date: 2010-06-19
    Presentation of work at congresses

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  • Mèrits docents d'especial qualitat

     Canal Corretger, Ramon
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  • Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    Design, Automation and Test in Europe
    p. 417-422
    DOI: 10.1109/DATE.2010.5457167
    Presentation's date: 2010-03-08
    Presentation of work at congresses

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    With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit performance are likely to suffer the most from this phenomena. While Statistical static timing analysis (SSTA) is used extensively for this purpose, it does not account for dynamic conditions during operation. In this paper, we present a multivariate regression based technique that computes the propagation delay of circuits subject to manufacturing process variations in the presence of temporal variations like temperature. It can be used to predict the dynamic behavior of circuits under changing operating conditions. The median error between the proposed model and circuit-level simulations is below 5%. With this model, we ran a study of the effect of temperature on access time delays for 500 cache samples. The study was run in 0.557 seconds, compared to the 20h and 4min of the SPICE simulation achieving a speedup of over 1??105. As a case study, we show that the access times of caches can vary as much as 2.03?? at high temperatures in future technologies under process variations.

  • TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS

     Moll Echeto, Francesc de Borja; Figueras Pamies, Juan; Calomarde Palomino, Antonio; Aymerich Capdevila, Nivard; Vatajelu, Elena Ioana; Garcia Almudever, Carmen; Canal Corretger, Ramon; Pouyan, Peyman; Rubio Sola, Jose Antonio
    Competitive project

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  • TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS

     Canal Corretger, Ramon; Cruz Diaz, Josep-llorenç; Tubella Murgadas, Jordi; Gonzalez Colas, Antonio Maria
    Competitive project

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  • An hybrid eDRAM/SRAM macrocell to implement first-level data caches

     Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Lorente, Vicente; Canal Corretger, Ramon; López, Pedro; Duato, José
    IEEE/ACM International Symposium on Microarchitecture
    p. 213-221
    DOI: /doi.acm.org/10.1145/1669112.1669140
    Presentation's date: 2009-12-14
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    SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy since there are no paths within the cell from Vdd to ground. Recently, DRAM cells have been embedded in logic-based technology, thus overcoming the speed limit of typical DRAM cells. In this paper we propose an n-bit macrocell that implements one static cell, and n-1 dynamic cells. This cell is aimed at being used in an n-way set-associative first-level data cache. Our study shows that in a four-way set-associative cache with this macrocell compared to an SRAM based with the same capacity, leakage is reduced by about 75% and area more than half with a minimal impact on performance. Architectural mechanisms have also been devised to avoid refresh logic. Experimental results show that no performance is lost when the retention time is larger than 50K processor cycles. In addition, the proposed delayed writeback policy that avoids refreshing performs a similar amount of writebacks than a conventional cache with the same organization, so no power wasting is incurred.

  • Microarquitectura i compiladors (ARCO)

     Tubella Murgadas, Jordi; Gonzalez Colas, Antonio Maria; Parcerisa Bundó, Joan Manuel; Canal Corretger, Ramon; Cruz Diaz, Josep-llorenç; Molina Clemente, Carlos Maria; Aliagas Castell, Carles; Aleta Ortega, Alexandre; Deb, Abhishek; Sreekar Shenoy, Govind; Pavlou, Demos; Herrero Abellanas, Enric; Yazdanpanah Ahmadabadi, Fahimeh; Bhagat, Indu; Lira Rueda, Javier; Lupon Navazo, Marc; Pons Sole, Marc; Ranjan, Rakesh; Ganapathy, Shrikanth; Jaksic, Zoran
    Competitive project

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  • Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria; Rubio, Antonio
    Date: 2009-09-07
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  • MICROARQUITECTURA I COMPILADORS (ARCO)

     Gibert Codina, Enric; Codina Viñas, Josep M; Magklis, Grigorios; Pons Solé, Marc; Parcerisa Bundó, Joan Manuel; Gonzalez Colas, Antonio Maria; Molina Clemente, Carlos; Aleta Ortega, Alexandre; Aliagas Castell, Carles; Cruz Diaz, Josep-llorenç; Canal Corretger, Ramon; Vera Rivera, Francisco Javier; Piñeiro Riobo, Jose Alejandro; Unsal, Osman Sabri; Tubella Murgadas, Jordi
    Competitive project

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  • 2009-SGR-1250 Arquitectura i Compiladors (ARCO)

     Tubella Murgadas, Jordi; Parcerisa Bundó, Joan Manuel; Gonzalez Colas, Antonio Maria; Canal Corretger, Ramon; Cruz Diaz, Josep-llorenç; Molina Clemente, Carlos; Aliagas Castell, Carles; Aleta Ortega, Alexandre
    Competitive project

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    Using coherence information and decay techniques to optimize L2 cache leakage in CMPs  Open access

     Monchiero, Matteo; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria
    International Conference on Parallel Processing
    p. 1-8
    DOI: 10.1109/ICPP.2009.28
    Presentation's date: 2009
    Presentation of work at congresses

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    This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this case, coherence must be enforced in all situations and specially when a line is turned off to save power. In particular, we introduce three techniques: the first one turns off the cache lines by using the coherence protocol invalidations, the second one is an implementation of a cache decay technique specific for coherent caches, the third one is a performance-optimized decay-based technique for coherent caches. Experimental results, carried out by using accurate performance/thermal/energy models, show that appreciable power savings can be achieved by properly designing a leakage optimization technique. We target a CMP composed of 4 cores and 1 to 8 MB of total cache. For 4MB, the proposed techniques show a 13%, 30%, and 21% energy reduction, respectively, at the cost of 0%, 8%, and 2% performance loss. For other cache sizes the behavior is qualitatively similar.

  • Distributed cooperative caching

     Herrero Abellanas, Enric; Gonzalez, José; Canal Corretger, Ramon
    International Conference on Parallel Architectures and Compilation Techniques
    p. 134-143
    DOI: /doi.acm.org/10.1145/1454115.1454136
    Presentation's date: 2008-10-25
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  • Architectural Level Power Simulator of the Memory Hierarchy of Chip Multiprocessors

     Herrero, Enric; González, José; Canal Corretger, Ramon
    Date: 2008-06
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  • Optimizing L2-Cache leakage in Chip Multiprocessors

     Monchiero, Matteo; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria
    Date: 2008-03
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  • El procés vist des d'AC

     Canal Corretger, Ramon
    Jornadas Docentes del Departamento de Arquitectura de Computadores
    p. 1-10
    Presentation's date: 2008-02-14
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  • Continguts de les assignatures de circuits (DM, DTC). Què fem? Què hauriem de fer?

     Canal Corretger, Ramon
    Jornadas Docentes del Departamento de Arquitectura de Computadores
    p. 1-10
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  • A Scalable and Power-Efficient Memory Hierarchy for Multicore Architectures

     Herrero Abellanas, Enric; González, José; Canal Corretger, Ramon
    Intel European Research and Innovation Conference
    p. 44
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  • TIN2007-61763 Arquitectures i Compiladors 2

     Gonzalez Colas, Antonio Maria; Canal Corretger, Ramon
    Competitive project

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