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Canal Corretger, Ramon

Total activity: 133
Areas of expertise
DRAM, Memory Design, Microarchitecture, Nanotechnology Circuit Design, Near and Subthreshold Architectures, Non-Volatile Memories, Processor Design, SRAM, Variability
h index
16
Professional category
University lecturer
Doctoral courses
Doctor per la Universitat Politècnica de Catalunya
University degree
Enginyer en Informàtica
Research group
ARCO - Microarchitecture and Compilers
Department
Department of Computer Architecture
School
Barcelona School of Informatics (FIB)
E-mail
rcanalac.upc.edu
Contact details
UPC directory Open in new window
Orcid
0000-0003-4542-204X Open in new window
ResearcherID
E-7775-2014 Open in new window
Scopus Author ID
7004495853 Open in new window
Links of interest
Personal webpage Open in new window

Scientific and technological production

1 to 50 of 133 results
 
  • Feasibility of Embedded DRAM Cells on FinFET Technology

     Amat, Esteve; Calomarde, A.; Moll, F.; Canal, R.; Rubio, A.
    IEEE transactions on computers
    Vol. 65, num. 4, p. 1068-1074
    DOI: 10.1109/TC.2014.2375204
    Date of publication: 2016-04-01
    Journal article
  • A detailed methodology to compute Soft Error Rates in advanced technologies

     Riera, M.; Canal, R.; Abella, J.; Gonzalez, A.
    Design, Automation & Test in Europe Conference & Exhibition
    p. 217-222
    Presentation's date: 2016-03
    Presentation of work at congresses
  • Cache Memory Design in the FinFET Era  Open access

     Jaksic, Z.
    Universitat Politècnica de Catalunya
    Theses
  • REEM: failure/non-failure region estimation method for SRAM yield analysis

     Rana, M.; Canal, R.
    IEEE International Conference on Computer Design
    p. 36-41
    DOI: 10.1109/ICCD.2014.6974659
    Presentation's date: 2014-10
    Presentation of work at congresses
  • Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm

     Amat, Esteve; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, A.
    Microelectronics journal
    Vol. 45, num. 10, p. 1342-1347
    DOI: 10.1016/j.mejo.2013.12.001
    Date of publication: 2014-10-01
    Journal article
  • Suitability of the FinFET 3T1D cell beyond 10 nm

     Amat, Esteve; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, A.
    IEEE transactions on nanotechnology
    Vol. 13, num. 5, p. 926-932
    DOI: 10.1109/TNANO.2014.2332180
    Date of publication: 2014-09-01
    Journal article
  • Cross-layer early reliability evaluation: Challenges and promises

     Stefano Di Carlo; Vallero, A.; Gizopoulos, D.; Di Natale, G.; Gonzalez, A.; Canal, R.; Mariani, R.; Pipponzi, M.; Grasset, A.; Bonnot, P.; Reichenbach, F.; Rafiq, G.; Loekstad, T.
    IEEE International On-Line Testing Symposium
    p. 228-233
    DOI: 10.1109/IOLTS.2014.6873704
    Presentation's date: 2014-07-07
    Presentation of work at congresses
  • Reliability In The Face of Variability in Nanometer Embedded Memories  Open access

     Ganapathy, S.
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses
  • INFORMER: an integrated framework for early-stage memory robustness analysis

     Ganapathy, S.; Canal, R.; Alexandrescu, D.; Costenaro, E.; Gonzalez, A.; Rubio, A.
    Design, Automation & Test in Europe Conference & Exhibition
    p. 1-4
    DOI: 10.7873/DATE2014.046
    Presentation's date: 2014-03-24
    Presentation of work at congresses
  • SSFB: a highly-efficient and scalable simulation reduction technique for SRAM yield analysis

     Rana, M.; Canal, R.
    Design, Automation & Test in Europe Conference & Exhibition
    p. 1-6
    DOI: 10.7873/DATE2014.045
    Presentation's date: 2014-03-24
    Presentation of work at congresses
  • DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy

     Jaksic, Z.; Canal, R.
    Design, Automation & Test in Europe Conference & Exhibition
    DOI: 10.7873/DATE2014.094
    Presentation's date: 2014-03
    Presentation of work at congresses
  • Variability impact on on-chip memory data paths  Open access

     Amat, Esteve; Calomarde, A.; Canal, R.; Rubio, A.
    European Workshop on CMOS Variability
    DOI: 10.1109/VARI.2014.6957086
    Presentation's date: 2014
    Presentation of work at congresses
    Access to the full text
  • iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches  Open access

     Ganapathy, S.; Canal, R.; Gonzalez, A.; Rubio, A.
    IEEE International Conference on Computer Design
    p. 68-74
    DOI: 10.1109/ICCD.2014.6974664
    Presentation's date: 2014
    Presentation of work at congresses
    Access to the full text
  • Microarquitectura y Compiladores para Futuros Procesadores III

     Gonzalez, A.; Parcerisa, Joan-Manuel; Canal, R.; Cruz, J.; Bosque, A.; Zyulkyarov, F.; Sanchez-Pedreño, D.; Molina, C.; Aliagas, C.; García-Guirado, A.; Tubella, J.
    Competitive project
  • Impact of finfet and III-V/Ge technology on logic and memory cell behavior

     Amat, E.; Calomarde, A.; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, A.
    IEEE transactions on device and materials reliability
    Vol. 14, num. 1, p. 1-15
    DOI: 10.1109/TDMR.2013.2291410
    Date of publication: 2013-11-20
    Journal article
  • Thread row buffers: Improving memory performance isolation and throughput in multiprogrammed environments

     Herrero, E.; González, J.; Canal, R.; Tullsen, D.
    IEEE transactions on computers
    Vol. 62, num. 9, p. 1879-1892
    DOI: 10.1109/TC.2012.173
    Date of publication: 2013-09
    Journal article
  • Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells

     Amat, Esteve; Garcia, C.; Aymerich, N.; Rubio, A.; Canal, R.
    IEEE International Midwest Symposium on Circuits and Systems
    p. 81-84
    DOI: 10.1109/MWSCAS.2013.6674590
    Presentation's date: 2013-08-05
    Presentation of work at congresses
  • An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

     Jing, N.; Shen, Y.; Lu, Y.; Ganapathy, S.; Mao, Z.; Guo, M.; Canal, R.; Liang, X.
    Annual International Symposium on Computer Architecture
    p. 344-355
    DOI: 10.1145/2485922.2485952
    Presentation's date: 2013-06
    Presentation of work at congresses
  • Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes

     Lorente, V.; Valero, A.; Sahuquillo, J.; Petit, S.; Canal, R.; López, P.; Duato, J.
    Design, Automation & Test in Europe Conference & Exhibition
    p. 83-88
    DOI: 10.7873/DATE.2013.031
    Presentation's date: 2013-03-20
    Presentation of work at congresses
  • Effectiveness of hybrid recovery techniques on parametric failures

     Ganapathy, S.; Canal, R.; Gonzalez, A.; Rubio, A.
    International Symposium on Quality Electronic Design
    p. 258-264
    DOI: 10.1109/ISQED.2013.6523620
    Presentation's date: 2013-03
    Presentation of work at congresses
  • Impact of FinFET technology introduction in the 3T1D-DRAM memory cell

     Amat, Esteve; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, A.
    IEEE transactions on device and materials reliability
    Vol. 13, num. 1, p. 287-292
    DOI: 10.1109/TDMR.2013.2238542
    Date of publication: 2013-01-09
    Journal article
  • Variability mitigation mechanisms in scaled 3T1D DRAM memories to 22nm and beyond

     Amat, Esteve; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, A.
    IEEE transactions on device and materials reliability
    Vol. 13, num. 1, p. 103-109
    DOI: 10.1109/TDMR.2012.2217497
    Date of publication: 2013
    Journal article
  • FinFET and III-V/Ge technology impact on 3T1D cell behavior  Open access

     Amat, Esteve; Calomarde, A.; Almudever, C.G.; Aymerich, N.; Canal, R.; Rubio, A.
    Intel Ireland Research Conference
    Presentation's date: 2013
    Presentation of work at congresses
    Access to the full text
  • FinFET introduction in 3T1D-DRAM memory cells

     Amat, Esteve; Almudever, C.G.; Aymerich, N.; Canal, R.; Rubio, A.
    Conference on Design of Circuits and Integrated Systems
    DOI: 10.1109/TDMR.2013.2238542
    Presentation's date: 2013
    Presentation of work at congresses
  • Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations

     Jaksic, Z.; Canal, R.
    IEEE transactions on electron devices
    Vol. 60, num. 1, p. 49-55
    DOI: 10.1109/TED.2012.2226095
    Date of publication: 2012-12
    Journal article
  • Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs

     Jaksic, Z.; Canal, R.
    IEEE International Conference on Computer Design
    p. 309-314
    DOI: 10.1109/ICCD.2012.6378657
    Presentation's date: 2012-10-02
    Presentation of work at congresses
  • A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance

     Ganapathy, S.; Canal, R.; Alexandrescu, D.; Costenaro, E.; Gonzalez, A.; Rubio, A.
    IEEE International Conference on Computer Design
    p. 472-477
    DOI: 10.1109/ICCD.2012.6378681
    Presentation's date: 2012-10-02
    Presentation of work at congresses
  • Impact of bulk/SOI 10nm FinFETs on 3T1D-DRAM cell performance

     Amat, Esteve; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, A.
    International Conference on Solid-State and Integrated Circuit Technology
    p. 1-3
    DOI: 10.1109/ICSICT.2012.6466713
    Presentation's date: 2012-10
    Presentation of work at congresses
  • A Novel variation-tolerant 4T-DRAM with enhance soft-error tolerance

     Ganapathy, S.; Canal, R.; Alexandrescu, D.; Costenaro, E.; Gonzalez, A.; Rubio, A.
    IEEE International Conference on Computer Design
    p. 472-477
    DOI: 10.1109/ICCD.2012.6378681
    Presentation's date: 2012-09-30
    Presentation of work at congresses
  • Variability mitigation mechanisms in scaled 3T1D-DRAM memories to 22 nm and beyond

     Amat, Esteve; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, A.
    IEEE transactions on device and materials reliability
    Vol. 13, num. 1, p. 103-109
    DOI: 10.1109/TDMR.2012.2217497
    Date of publication: 2012-09-06
    Journal article
  • Analysis of FinFET technology on memories

     Amat, E.; ASenov, A.; Canal, R.; Cheng, B.; Cruz, J.; Jaksic, Z.; Miranda, M.; Rubio, A.; Zuber, P.
    IEEE International On-Line Testing Symposium
    p. 169
    DOI: 10.1109/IOLTS.2012.6313866
    Presentation's date: 2012-06-29
    Presentation of work at congresses
  • Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells

     Aymerich, N.; Ganapathy, S.; Rubio, A.; Canal, R.; Gonzalez, A.
    Integration. The VLSI journal
    Vol. 45, num. 3, p. 246-252
    DOI: 10.1016/j.vlsi.2011.11.014
    Date of publication: 2012-06
    Journal article
  • Enhancing 6T SRAM cell stabilitty by back gate biasing techniques for 10nm SOI FinFETs under process and environmental variations

     Jaksic, Z.; Canal, R.
    International Conference Mixed Design of Integrated Circuits and Systems
    p. 103-108
    Presentation's date: 2012-05-26
    Presentation of work at congresses
  • Strain relevance on the improvement of the 3T1D cell performance

     Amat, Esteve; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, A.
    International Conference Mixed Design of Integrated Circuits and Systems
    p. 120-123
    Presentation's date: 2012-05-26
    Presentation of work at congresses
  • IEEE On-Line Testing Symposium 2012

     Cruz, J.; Ganapathy, S.; Jaksic, Z.; Canal, R.
    Competitive project
  • Distributed cooperative caching: an energy efficient memory scheme for chip multiprocessors

     Herrero, E.; González, J.; Canal, R.
    IEEE transactions on parallel and distributed systems
    Vol. 23, num. 5, p. 853-861
    DOI: 10.1109/TPDS.2011.200
    Date of publication: 2012-05
    Journal article
  • Process variability in sub-16nm bulk CMOS technology  Open access

     Rubio, A.; Figueras, J.; Vatajelu, E.; Canal, R.
    Date: 2012-03-01
    Report
    Access to the full text
  • Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm  Open access  awarded activity

     Amat, Esteve; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, A.
    Conference on Design of Circuits and Integrated Systems
    p. 1-5
    Presentation's date: 2012
    Presentation of work at congresses
    Access to the full text
  • TRAMS Project: variability and reliability of SRAM memories in sub-22nm bulk-CMOS technologies

     Canal, R.; Rubio, A.; ASenov, A.; Brown, A.; Miranda, M.; Zuber, P.; Gonzalez, A.; Vera, X.
    Procedia Computer Science
    Vol. 7, p. 148-149
    DOI: 10.1016/j.procs.2011.09.010
    Date of publication: 2011-12-22
    Journal article
  • On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches

     Ganapathy, S.; Canal, R.; Gonzalez, A.; Rubio, A.
    Date: 2011-12-05
    Report
  • Adaptive Memory Hierarchies For Next Generation Tiled Microarchitectures  Open access  awarded activity

    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells

     Aymerich, N.; Ganapathy, S.; Rubio, A.; Canal, R.; Gonzalez, A.
    ACM Great Lakes Symposium on VLSI
    p. 227-282
    DOI: 10.1145/1973009.1973065
    Presentation's date: 2011-05-18
    Presentation of work at congresses
  • Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors  Open access

     Ganapathy, S.; Canal, R.; Gonzalez, A.; Rubio, A.
    Date: 2011-04-15
    Report
    Access to the full text
  • Cooperative caching for clip multiprocessors

     , J.; Herrero, E.; Canal, R.; Sohi, G.
    Date of publication: 2011
    Book chapter
    Image
  • Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

     Ganapathy, S.; Canal, R.; Gonzalez, A.; Rubio, A.
    IEEE International Conference on Computer Design
    p. 332-338
    DOI: 10.1109/ICCD.2011.6081420
    Presentation's date: 2011
    Presentation of work at congresses
  • TRAMS Project: variability and reliability of SRAM memories in sub-22 nm Bulk-CMOS technologies

     Canal, R.; Rubio, A.; ASenov, A.; Brown, A.; Miranda, M.; Zuber, P.; Gonzalez, A.; Vera, X.
    European Future Technologies Conference and Exhibition
    p. 148-149
    DOI: 10.1016/j.procs.2011.09.010
    Presentation's date: 2011
    Presentation of work at congresses
  • New reliability mechanisms in memory design for sub-22nm technologies

     Aymerich, N.; Brown, A.; Canal, R.; Cheng, B.; Figueras, J.; Gonzalez, A.; Herrero, E.; Markov, S.; Miranda, M.; Pouyan, P.; Ramirez, T.; Rubio, A.; Vatajelu, I.; Vera, X.; Wang, W.; Zuber, P.; ASenov, A.
    IEEE International On-Line Testing Symposium
    p. 111-114
    DOI: 10.1109/IOLTS.2011.5993820
    Presentation of work at congresses
  • MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES II

     Parcerisa, Joan-Manuel; Canal, R.; Tubella, J.; Cruz, J.; Gonzalez, A.
    Competitive project
  • vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells  Open access

     Ganapathy, S.; Canal, R.; Gonzalez, A.; Rubio, A.
    Date: 2010-09-05
    Report
    Access to the full text
  • Power-efficient spilling techniques for chip multiprocessors

     Herrero, E.; González, J.; Canal, R.
    International European Conference on Parallel and Distributed Computing
    p. 256-267
    DOI: 10.1007/978-3-642-15277-1_25
    Presentation's date: 2010-09-02
    Presentation of work at congresses