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  • Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures  Open access

     Alvarez, Ll.; Vilanova, L.; Moreto, M.; Casas, M.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.; Valero, M.
    Annual International Symposium on Computer Architecture
    p. 720-732
    DOI: 10.1145/2749469.2750411
    Presentation's date: 2015-06-15
    Presentation of work at congresses
    Access to the full text
  • Hardware-software coherence protocol for the coexistence of caches and local memories  Open access

     Alvarez, L.; Vilanova, L.; Gonzalez, M.; Martorell, X.; Navarro, N.; Ayguade, E.
    IEEE transactions on computers
    Vol. 64, num. 1, p. 152-165
    DOI: 10.1109/TC.2013.194
    Date of publication: 2015-01-01
    Journal article
    Access to the full text
  • Energy Characterization Methodologies for CMP/SMT Processor Systems

    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • Models de Programacio i Entorns d'eXecució PARal.lels

     Becerra, Y.; Carrera, D.; Corbalan, J.; Cortes, A.; Costa, J.; Farreras, M.; Gil, Marisa; Gonzalez, M.; Guitart, J.; Herrero, J.; Labarta, J.; Martorell, X.; Navarro, Nacho; Nin, J.; Torres, J.; Tous, R.; Utrera, G.; Ayguade, E.
    Competitive project
  • A systematic methodology to generate decomposable and responsive power models for CMPs

     Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    IEEE transactions on computers
    Vol. 62, num. 7, p. 1289-1302
    DOI: 10.1109/TC.2012.97
    Date of publication: 2013-07
    Journal article
  • Systematic energy characterization of CMP/SMT processor systems via automated micro-benchmarks  Open access

     Bertran, R.; Buyuktosunoglu, A.; Gupta, M.; Gonzalez, M.; Bose, P.
    Annual IEEE/ACM International Symposium on Microarchitecture
    p. 199-211
    Presentation's date: 2012-12-01
    Presentation of work at congresses
    Access to the full text
  • Hardware-software coherence protocol for the coexistence of caches and local memories

     Alvarez, L.; Vilanova, L.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    International Conference for High Performance Computing, Networking, Storage and Analysis
    p. Article No. 89-
    DOI: 10.1109/TC.2013.194
    Presentation's date: 2012-11-07
    Presentation of work at congresses
  • Counter-based power modeling methods: top-down vs. bottom-up

     Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    The computer journal (Kalispell, Mont.)
    Vol. 56, num. 2, p. 198-213
    DOI: 10.1093/comjnl/bxs116
    Date of publication: 2012-08-24
    Journal article
  • Software caching techniques and hardware optimizations for on-chip local memories  Open access

    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • POTRA: a framework for building power models for next generation multicore architectures

     Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    ACM SIGMETRICS performance evaluation review
    Vol. 40, num. 1, p. 427-428
    DOI: 10.1145/2318857.2254827
    Date of publication: 2012-06
    Journal article
  • DMA-circular: an enhanced high level programmable DMA controller for optimized management of on-chip local memories

     Vujic, N.; Alvarez, L.; Gonzalez, M.; Martorell, X.; Ayguade, E.
    ACM International Conference on Computing Frontiers
    p. 113-122
    DOI: 10.1145/2212908.2212925
    Presentation's date: 2012-05-15
    Presentation of work at congresses
  • Energy accounting for shared virtualized environments under DVFS using PMC-based power models

     Bertran, R.; Becerra, Y.; Carrera, D.; Beltran, V.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Torres, J.; Ayguade, E.
    Future generation computer systems
    Vol. 28, num. 2, p. 457-468
    DOI: 10.1016/j.future.2011.03.007
    Date of publication: 2012-02
    Journal article
  • DMA++: on the fly data realignment for on-chip memories

     Vujic, N.; Cabarcas, F.; Gonzalez, M.; Alex Ramirez; Martorell, X.; Ayguade, E.
    IEEE transactions on computers
    Vol. 61, num. 2, p. 237-250
    DOI: 10.1109/TC.2010.255
    Date of publication: 2012-02
    Journal article
  • POTRA: a framework for building power models for next generation multicore architectures

     Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    ACM SIGMETRICS/PERFORMANCE joint International Conference on Measurement and Modeling of Computer Systems
    p. 427-428
    DOI: 10.1145/2254756.2254827
    Presentation's date: 2012
    Presentation of work at congresses
  • Design space exploration for aggressive core replication schemes in CMPs

     Álvarez, L.; Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    International Symposium on High Performance Distributed Computing
    p. 269-270
    DOI: 10.1145/1996130.1996169
    Presentation's date: 2011-06-08
    Presentation of work at congresses
  • Optimizing the exploitation of multicore processors and GPUs with OpenMP and OpenCL

     Planas, J.; Ferrer, R.; Bellens, P.; Duran, A.; Gonzalez, M.; Martorell, X.; Badia, R.M.; Ayguade, E.; Labarta, J.
    Lecture notes in computer science
    Vol. 6548, p. 215-229
    DOI: 10.1007/978-3-642-19595-2_15
    Date of publication: 2011
    Journal article
  • Accurate energy accounting for shared virtualized environments using PMC-based power modeling techniques

     Bertran, R.; Becerra, Y.; Carrera, D.; Beltran, V.; Gonzalez, M.; Martorell, X.; Torres, J.; Ayguade, E.
    ACM/IEEE International Conference on Grid Computing
    p. 1-8
    DOI: 10.1109/GRID.2010.5697889
    Presentation's date: 2010-10-27
    Presentation of work at congresses
  • Optimizing the exploitation of multicore processors and GPUs with OpenMP and OpenCL

     Ferrer, R.; Planas, J.; Bellens, P.; Duran, A.; Gonzalez, M.; Martorell, X.; Badia, R.M.; Ayguade, E.; Labarta, J.
    International Workshop on Languages and Compilers for Parallel Computing
    p. 215-229
    DOI: 10.1007/978-3-642-19595-2_15
    Presentation's date: 2010-10
    Presentation of work at congresses
  • Extending OpenMP to survive the heterogeneous multi-core era

     Ayguade, E.; Badia, R.M.; Bellens, P.; Ferrer, R.; Cabrera, D.; Duran, A.; Gonzalez, M.; Igual, Francisco D.; Jimenez, D.; Labarta, J.; Martinell, L.; Martorell, X.; Mayo, R.; Perez, Josep M.; Planas, J.; Quintana, E.
    International journal of parallel programming
    Vol. 38, num. 5-6, p. 440-459
    DOI: 10.1007/s10766-010-0135-4
    Date of publication: 2010-10
    Journal article
  • Parallel programming models for heterogeneous multicore architectures

     Ferrer, R.; Beltran, V.; Gonzalez, M.; Martorell, X.; Ayguade, E.; Badia, R.M.; Yeom, J.; Schneider, S.; Koukos, K.; Alvanos, M.; Nikolopoulos, D.S.; Bilas, A.
    IEEE micro
    Vol. 30, num. 5, p. 42-53
    DOI: 10.1109/MM.2010.94
    Date of publication: 2010-09-01
    Journal article
  • Decomposable and responsive power models for multicore processors using performance counters

     Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    International Conference for High Performance Computing, Networking, Storage and Analysis
    p. 147-158
    DOI: 10.1145/1810085.1810108
    Presentation's date: 2010-06-04
    Presentation of work at congresses
  • Towards accurate accounting of energy consumption in shared virtualized environments

     Bertran, R.; Gonzalez, M.; Becerra, Y.; Carrera, D.; Torres, J.; Ayguade, E.
    International Conference on Energy-Efficient Computing and Networking
    Presentation's date: 2010-04
    Presentation of work at congresses
  • Automatic prefetch and modulo scheduling transformations for the Cell BE architecture

     Vujic, N.; Gonzalez, M.; Martorell, X.; Ayguade, E.
    IEEE transactions on parallel and distributed systems
    Vol. 21, num. 4, p. 494-505
    DOI: 10.1109/TPDS.2009.97
    Date of publication: 2010-04
    Journal article
  • Local memory design space exploration for high-performance computing

     Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    The Computer journal (paper)
    Vol. 54, num. 5, p. 786-799
    DOI: 10.1093/comjnl/bxq026
    Date of publication: 2010-03-23
    Journal article
  • HiPEAC Paper Award

     Vujic, N.; Gonzalez, M.; Alex Ramirez; Cabarcas, F.; Martorell, X.; Ayguade, E.
    Award or recognition
  • Analysis of task offloading for accelerators

     Ferrer, R.; Beltran, V.; Gonzalez, M.; Martorell, X.; Ayguade, E.
    International Conference on High Performance Embedded Architectures & Compilers
    p. 322-336
    DOI: 10.1007/978-3-642-11515-8_24
    Presentation's date: 2010-01
    Presentation of work at congresses
  • DMA++: on the fly data realignment for on-chip memories

     Vujic, N.; Gonzalez, M.; Cabarcas, F.; Alex Ramirez; Martorell, X.; Ayguade, E.
    International Symposium on High-Performance Computer Architecture
    p. 1-12
    DOI: 10.1109/HPCA.2010.5463057
    Presentation's date: 2010
    Presentation of work at congresses
  • Adaptive and speculative memory consistency support for multi-core architectures with on-chip local memories

     Vujic, N.; Álvarez, Lluc; Gonzalez, M.; Martorell, X.; Ayguade, E.
    International Workshop on Languages and Compilers for Parallel Computing
    p. 218-232
    DOI: 10.1007/978-3-642-13374-9_15
    Presentation's date: 2009-10
    Presentation of work at congresses
  • MPEXPAR: MODELS DE PROGRAMACIO I ENTORNS D'EXECUCIO PARAL·LELS

     Nou, R.; Gonzalez, M.; Gil, Marisa; Navarro, Nacho; Sirvent, R.; Guitart, J.; Carrera, D.; Martorell, X.; Herrero, J.; Torres, J.; Badia, R.M.; Becerra, Y.; Cortes, A.; Corbalan, J.; Costa, J.; Farreras, M.; Alonso, J.; Tejedor, E.; Labarta, J.; Ayguade, E.
    Competitive project
  • Speeding up distributed MapReduce applications using hardware accelerators  Open access

     Becerra, Y.; Beltran, V.; Carrera, D.; Gonzalez, M.; Torres, J.; Ayguade, E.
    International Conference on Parallel Processing
    p. 42-49
    DOI: 10.1109/ICPP.2009.59
    Presentation's date: 2009-09-22
    Presentation of work at congresses
    Access to the full text
  • Achieving high memory performance from heterogeneous architectures with the SARC programming model

     Ferrer, R.; Beltran, V.; Gonzalez, M.; Martorell, X.; Ayguade, E.
    Workshop on Memory Performance: dealing with Applications, Systems and Architecture
    p. 15-21
    DOI: doi.acm.org/10.1145/1621960.1621963
    Presentation's date: 2009-09
    Presentation of work at congresses
  • A proposal to extend the OpenMP tasking model for heterogeneous architectures

     Ayguade, E.; Badia, R.M.; Cabrera, D.; Duran, A.; Igual, Francisco D.; Jimenez, D.; Labarta, J.; Mayo, R.; Perez, Josep M.; Quintana, E.; Martorell, X.; Gonzalez, M.
    International Workshop on OpenMP
    p. 154-167
    DOI: 10.1007/978-3-642-02303-3
    Presentation's date: 2009-06-03
    Presentation of work at congresses
  • Laboratorio de Introducción a los Computadores: funcionamiento y dificultades docentes

     Navarro, J.; Cruz, J.; Faúndez, M.; Gonzalez, M.; Manso, O.; Muntés, V.; Palomar, O.; Rodero, I.; Sanchez, F.; Sole, M.
    Jornades de Docència del Departament d'Arquitectura de Computadors
    p. 1-20
    Presentation's date: 2009-02
    Presentation of work at congresses
  • Hybrid Access-Specific Software Cache Techniques for the Cell BE Architecture

     Gonzalez, M.
    Parallel Architectures and Compilation Techniques
    Presentation's date: 2008-10-29
    Presentation of work at congresses
  • Hybrid Access-Specific Software Cache Techniques for the Cell BE Architecture

     Gonzalez, M.
    International Conference on Parallel Architectures and Compilation Techniques
    Presentation's date: 2008-10-25
    Presentation of work at congresses
  • OPTIMIZED CODE GENERATION TARGETING A HIGH LOCALITY SOFTWARE CACHE

     Gonzalez, M.; Tong, C.; Eichenberger, A.; Zera, S.; Kathryn, O.; O'brien, K.; Zhang, T.
    Date of request: 2008-10-02
    Invention patent
  • Evaluation of memory performance on the cell BE with the SARC programming model

     Ferrer, R.; Gonzalez, M.; Federico, S.; Martorell, X.; Ayguade, E.
    Workshop on Memory Performance: dealing with Applications, Systems and Architecture
    p. 77-84
    DOI: 10.1145/1509084.1509095
    Presentation's date: 2008-10
    Presentation of work at congresses
  • Hybrid access-specific software cache techniques for the cell BE architecture

     Gonzalez, M.; Vujic, N.; Martorell, X.; Ayguade, E.; Eichenberger, A.; Chen, T.; Sura, Z.; Zhang, T.; O'Brien, K.; O’Brien, K.
    International Conference on Parallel Architectures and Compilation Techniques
    p. 292-302
    DOI: 10.1145/1454115.1454156
    Presentation's date: 2008-10
    Presentation of work at congresses
  • A novel asynchronous software cache implementation for the Cell-BE processor

     Balart, J.; Gonzalez, M.; Martorell, X.; Ayguade, E.; Sura, Z.; Chen, T.; Zhang, T.; O'Brien, K.
    Lecture notes in computer science
    Vol. 5234, num. 1, p. 125-140
    DOI: 10.1007/978-3-540-85261-2_9
    Date of publication: 2008-10
    Journal article
  • Prefetching Irregular References for Software Cache on Cell

     Gonzalez, M.
    International Symposium on Code Generation and Optimization
    Presentation's date: 2008-04-06
    Presentation of work at congresses
  • DYNAMICALLY CONTROLLING A PREFETCHING RANGE OF A SOFTWARE CONTROLLED CACHE

     Gonzalez, M.; Tong, C.; Zhang, T.; Zehra, S.
    Date of request: 2008-04-02
    Invention patent
  • PREFETCHING IRREGULAR DATA REFERENCES FOR SOFTWARE CONTROLLED CACHE

     Gonzalez, M.; Tong, C.; Zhang, T.; Zehra, S.
    Date of request: 2008-04-02
    Invention patent
  • REDUCING CACHE POLLUTION OF A SOFTWARE CONTROLLED CACHE

     Gonzalez, M.
    Date of request: 2008-04-02
    Invention patent
  • EFFICIENT SOFTWARE CACHE ACCESSING WITH HANDLING REUSE

     Gonzalez, M.
    Date of request: 2008-04-02
    Invention patent
  • Data transfer optimized software cache for irregular memory references

     Gonzalez, M.; Martorell, X.; Ayguade, E.; Eichenberger, A.; Tong, C.; Zehra, S.; Zhang, T.; Kathryn, O.; O'brien, K.
    Date of request: 2008-03-28
    Invention patent
  • DATA TRANSFER OPTIMIZED SOFTWARE CACHE FOR REGULAR MEMORY REFERENCES

     Gonzalez, M.; Martorell, X.; Ayguade, E.; Tong, C.; Eichenberger, A.; Zera, S.; Kathryn, O.; O'brien, K.; Zhang, T.
    Date of request: 2008-03-28
    Invention patent
  • Automatic pre-fetch and modulo scheduling transformations for the Cell BE architecture

     Vujic, N.; Gonzalez, M.; Martorell, X.; Ayguade, E.
    Lecture notes in computer science
    Vol. 5335, p. 31-46
    DOI: 10.1007/978-3-540-89740-8_3
    Date of publication: 2008-01
    Journal article
  • Prefetching Irregular References for Software Cache on Cell

     Tong, C.; Zhang, T.; Zehra, S.; Gonzalez, M.; Kathryn, O.; O'brien, K.
    International Symposium on Code Generation and Optimization
    p. 155-164
    Presentation of work at congresses
  • A novel asynchronous software cache implementation for the Cell-BE processor

     Balart, J.; Gonzalez, M.; Martorell, X.; Ayguade, E.; Zehra, S.; Tong, C.; Zhang, T.; O'brien, K.; Kathryn, O.
    Workshop on Languages and Compilers for Parallel Computing
    p. 125-140
    DOI: 10.1007/978-3-540-85261-2_9
    Presentation's date: 2007-10
    Presentation of work at congresses
  • A proposal for error handling in OpenMP

     Duran, A.; Ferrer, R.; Costa, J.; Gonzalez, M.; Martorell, X.; Ayguade, E.; Labarta, J.
    International journal of parallel programming
    Vol. 35, num. 4, p. 393-416
    Date of publication: 2007-08
    Journal article