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  • Analysis of the Task Superscalar architecture hardware design

     Yazdanpanah Ahmadabadi, Fahimeh; Jimenez Gonzalez, Daniel; Alvarez Martinez, Carlos; Etsion, Yoav; Badia Sala, Rosa Maria
    International Conference on Computational Science
    Presentation's date: 2013-06
    Presentation of work at congresses

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    In this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks in the out-of-order manner. In this paper, we present a base implementation of the Task Superscalar architecture, as well as a new design with improved performance. We study the behavior of processing some dependent and non-dependent tasks with both base and improved hardware designs and present the simulation results compared with the results of the runtime implementation.

  • FPGA-based prototype of the task superscalar architecture

     Yazdanpanah Ahmadabadi, Fahimeh; Jimenez Gonzalez, Daniel; Alvarez Martinez, Carlos; Etsion, Yoav; Badia Sala, Rosa Maria
    HiPEAC Workshop on Reconfigurable Computing
    Presentation's date: 2013-01-21
    Presentation of work at congresses

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    In this paper, we present the first hardware implementation of a prototype of the Task Superscalar architecture; an experimental task-based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks out-of-order. The implemented hardware is based on a distributed design that can op erate in parallel and is easily scalable to manage hundreds of cores in the same way that Out-of-Order architectures manage functional units. Our prototype operates at near 150 Mhz, fits in a current commercial FPGA board, and can maintain up to 1024 in-ight tasks, managing the data dependencies in few cycles.

  • Automatic design exploration framework for multicores with reconfigurable accelerators

     González, Cecilia Noemí; Isikawa, Haruku; Hayashi, Akihiro; Jimenez Gonzalez, Daniel; Alvarez Martinez, Carlos; Kimura, Keiji; Kasahara, Hironori
    HiPEAC Workshop on Reconfigurable Computing
    Presentation's date: 2013-01-21
    Presentation of work at congresses

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  • Accelerating an application domain with specialized functional units

     González, Cecilia Noemí; Sartor, Jennifer B.; Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel; Eeckhout, Lieven
    ACM transactions on architecture and code optimization
    Date of publication: 2013-12-14
    Journal article

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    Hardware specialization has received renewed interest recently as chips are hitting power limits. Chip designers of traditional processor architectures have primarily focused on general-purpose computing, partially due to time-to-market pressure and simpler design processes. But new power limits require some chip specialization. Although hardware configured for a specific application yields large speedups for low-power dissipation, its design is more complex and less reusable. We instead explore domain-based specialization, a scalable approach that balances hardware¿s reusability and performance efficiency. We focus on specialization using customized compute units that accelerate particular operations. In this article, we develop automatic techniques to identify code sequences from different applications within a domain that can be targeted to a new custom instruction that will be run inside a configurable specialized functional unit (SFU). We demonstrate that using a canonical representation of computations finds more common code sequences among applications that can be mapped to the same custom instruction, leading to larger speedups while specializing a smaller core area than previous pattern-matching techniques. We also propose new heuristics to narrow the search space of domain-specific custom instructions, finding those that achieve the best performance across applications. We estimate the overall performance achieved with our automatic techniques using hardware models on a set of nine media benchmarks, showing that when limiting the core area devoted to specialization, the SFU customization with the largest speedups includes both application- and domain-specific custom instructions. We demonstrate that exploring domain-specific hardware acceleration is key to continued computing system performance improvements.

  • OmpSs to OpenCL and to FPGAs

     Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel; Cabrera, Daniel; Martorell Bofill, Xavier; Ayguade Parra, Eduard
    International Workshop on Efficient Parallel Programming of Bioinformatics Applications on Heterogeneous HPC Platforms
    Presentation's date: 2012-06-28
    Presentation of work at congresses

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  • The task dependency analysis tool SSgrind

     Jimenez Gonzalez, Daniel; Alvarez Martinez, Carlos; Martorell Bofill, Xavier; Ayguade Parra, Eduard
    International Workshop on Efficient Parallel Programming of Bioinformatics Applications on Heterogeneous HPC Platforms
    Presentation's date: 2012-06-28
    Presentation of work at congresses

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  • The Smith-Waterman experience

     Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel
    International Workshop on Efficient Parallel Programming of Bioinformatics Applications on Heterogeneous HPC Platforms
    Presentation's date: 2012-06-25
    Presentation of work at congresses

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  • OmpSs to FPGA and overview of applications

     Jimenez Gonzalez, Daniel; Alvarez Martinez, Carlos; Martorell Bofill, Xavier; Ayguade Parra, Eduard
    International Workshop on Efficient Parallel Programming of Bioinformatics Applications on Heterogeneous HPC Platforms
    Presentation's date: 2012-06-25
    Presentation of work at congresses

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  • Cell-Dock: high-performance protein-protein docking

     Pons, Carles; Jimenez Gonzalez, Daniel; González Álvarez, Cecilia; Servat Gelabert, Harald; Cabrera Benitez, Daniel; Aguilar, Xavier; Fernández Recio, Juan
    Bioinformatics
    Date of publication: 2012-09
    Journal article

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    The application of docking to large-scale experiments or the explicit treatment of protein flexibility are part of the new challenges in structural bioinformatics that will require large computer resources and more efficient algorithms. Highly optimized FFT approaches are broadly used in docking programs but their optimal code implementation leaves hardware acceleration as the only option to significantly reduce the computational cost of these tools. In this work we present Cell-Dock, an FFT-based docking algorithm adapted to the Cell BE processor. We show that Cell-Dock runs faster than FTDock with maximum speedups of above 200x, while achieving results of similar quality

  • Automatic generation and testing of application specific hardware accelerators on a new reconfigurable OpenSPARC platform

     González Álvarez, Cecilia; Fernández, Mikel; Jimenez Gonzalez, Daniel; Alvarez Martinez, Carlos; Martorell Bofill, Xavier
    HiPEAC Workshop on Reconfigurable Computing
    Presentation's date: 2011-01-23
    Presentation of work at congresses

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  • Plataforma docent per a treballar amb una FPGA

     Jimenez Gonzalez, Daniel; Alvarez Martinez, Carlos
    Jornades de Docència del Departament d'Arquitectura de Computadors
    Presentation's date: 2010-02
    Presentation of work at congresses

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  • GPFPGA: entorno para la generación automática de códigos HDL portables entre FPGAs

     Jimenez Gonzalez, Daniel; Sánchez Fernández, Raúl; Alvarez Martinez, Carlos; Morillo Pozo, Julian David; Cabrera, Daniel; Martorell Bofill, Xavier; Ayguade Parra, Eduard
    Jornadas de Computación Reconfigurable y Aplicaciones
    Presentation's date: 2010-09
    Presentation of work at congresses

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  • Drug design on the Cell BE

     González Álvarez, Cecilia; Servat Gelabert, Harald; Cabrera Benitez, Daniel; Aguilar, Xavier; Pons, Carles; Fernánez Recio, Juan; Jimenez Gonzalez, Daniel
    Date of publication: 2010-12
    Book chapter

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  • Dataflow computing model

     Yazdanpanah Ahmadabadi, Fahimeh; Jimenez Gonzalez, Daniel; Alvarez Martinez, Carlos
    Date: 2010-07
    Report

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  • Extending OpenMP to survive the heterogeneous multi-core era

     Ayguade Parra, Eduard; Badia Sala, Rosa Maria; Bellens, Pieter; Cabrera, Daniel; Duran González, Alejandro; Ferrer, Roger; Gonzalez Tallada, Marc; Igual, Francisco D.; Jimenez Gonzalez, Daniel; Labarta Mancho, Jesus Jose; Martinell, Lluis; Martorell Bofill, Xavier; Mayo, Rafael; Pérez Cáncer, Josep Maria; Planas, Judit; Quintana Ortí, Enrique Salvador
    International journal of parallel programming
    Date of publication: 2010-10
    Journal article

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    This paper advances the state-of-the-art in programming models for exploiting task-level parallelism on heterogeneous many-core systems, presenting a number of extensions to the OpenMP language inspired in the StarSs programming model. The proposed extensions allow the programmer to write portable code easily for a number of different platforms, relieving him/her from developing the specific code to off-load tasks to the accelerators and the synchronization of tasks. Our results obtained from the StarSs instantiations for SMPs, theCell, and GPUs report reasonable parallel performance. However, the real impact of our approach in is the productivity gains it yields for the programmer.

  • Aprendizaje cooperativo en cursos multidisciplinares  Open access

     Alvarez Martinez, Carlos; Lopez Alvarez, David; Jimenez Gonzalez, Daniel; Alonso López, Javier
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation's date: 2009
    Presentation of work at congresses

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    La enseñanza de contenidos técnicos en grupos multidisciplinares es una tarea compleja debido a la diversidad de los conocimientos iniciales de los alumnos implicados. Sin embargo esta dificultad puede llegar a convertirse en una poderosa herramienta. En este artículo se presenta la experiencia obtenida durante una asignatura de software libre impartida a un grupo multidisciplinar formado por alumnos de distintas carreras técnicas. La base de nuestra propuesta es obligar a los estudiantes a cooperar forzando grupos compuestos por alumnos de diferentes carreras. Este tipo de agrupación obliga a los alumnos a realizar trabajo cooperativo y aprendizaje entre iguales, lo que les permite desarrollar habilidades tanto técnicas como profesionales. Nuestros resultados muestran que con este enfoque se consiguen buenos resultados tanto en el aprendizaje como en la aceptación por parte de los alumnos de la asignatura y del método de enseñanza.

  • Metodologí­a para la generación y evaluación automática de hardware específico

     González, Cecilia; Jimenez Gonzalez, Daniel; Martorell Bofill, Xavier; Alvarez Martinez, Carlos; Gaydadjiev, Georgi
    Jornadas de Paralelismo
    Presentation's date: 2009-09
    Presentation of work at congresses

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  • A proposal to extend the OpenMP tasking model for heterogeneous architectures

     Ayguade Parra, Eduard; Badia Sala, Rosa Maria; Cabrera, Daniel; Duran Gonzalez, Alejandro; Igual, Francisco D.; Jimenez Gonzalez, Daniel; Labarta Mancho, Jesus Jose; Mayo, Rafael; Pérez, Josep M.; Quintana Ortí, Enrique Salvador; Martorell Bofill, Xavier; Gonzalez Tallada, Marc
    International Workshop on OpenMP
    Presentation's date: 2009-06-03
    Presentation of work at congresses

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  • Aprendizaje cooperativo en grupos multidisciplinares  Open access

     Alvarez Martinez, Carlos; Lopez Alvarez, David; Jimenez Gonzalez, Daniel; Alonso López, Javier
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation's date: 2009-07
    Presentation of work at congresses

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    La enseñanza de contenidos técnicos en grupos multidisciplinares es una tarea compleja debido a la diversidad de los conocimientos iniciales de los alumnos implicados. Sin embargo esta dificultad puede llegar a convertirse en una poderosa herramienta. En este artículo se presenta la experiencia obtenida durante una asignatura de software libre impartida a un grupo multidisciplinar formado por alumnos de distintas carreras técnicas. La base de nuestra propuesta es obligar a los estudiantes a cooperar forzando grupos compuestos por alumnos de diferentes carreras. Este tipo de agrupación obliga a los alumnos a realizar trabajo cooperativo y aprendizaje entre iguales, lo que les permite desarrollar habilidades tanto técnicas como profesionales. Nuestros resultados muestran que con este enfoque se consiguen buenos resultados tanto en el aprendizaje como en la aceptación por parte de los alumnos de la asignatura y del método de enseñanza.

  • Una imagen vale más que mil palabras

     Jimenez Gonzalez, Daniel; Alvarez Martinez, Carlos
    Jornades de Docència del Departament d'Arquitectura de Computadors
    Presentation's date: 2009-02
    Presentation of work at congresses

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  • Aprendizaje entre iguales con grupos multidisciplinares

     Alvarez Martinez, Carlos; Lopez Alvarez, David; Jimenez Gonzalez, Daniel; Alonso López, Javier
    Jornades de Docència del Departament d'Arquitectura de Computadors
    Presentation's date: 2009-02
    Presentation of work at congresses

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  • Preliminary work on a mechanism for testing a customized architecture

     González, Cecilia; Jimenez Gonzalez, Daniel; Martorell Bofill, Xavier; Alvarez Martinez, Carlos; Gaydadjiev, Georgi
    International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
    Presentation's date: 2009-07
    Presentation of work at congresses

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  • Access to the full text
    Fast evaluation methodology for automatic custom hardware prototyping  Open access

     González, Cecilia; Jimenez Gonzalez, Daniel; Martorell Bofill, Xavier; Alvarez Martinez, Carlos; Gaydadjiev, Georgi
    Workshop on Architectural Research Prototyping
    Presentation's date: 2009-06-20
    Presentation of work at congresses

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    Hardware customization for scientific applications has shown a big potential for reducing power consumption and increasing performance. In particular, the automatic generation of ISA extensions for General-Purpose Processors (GPPs) to accelerate domain-specific applications is an active field of research to accelerate. Those domain-specific accelerated processors are mostly evaluated in simulation environments due to technical and programmability issues while using real hardware. There is no automatic mechanism to test those custom units in a real hardware environment. In this paper we present a toolchain that can automatically identify candidate parts of the code suitable for reconfigurable hardware acceleration. We validate our toolchain using ClustalW.

  • ARQUITECTURA DE COMPUTADORS D'ALTRES PRESTACIONS (CAP)

     Jimenez Castells, Marta; Pericas Gleim, Miquel; Navarro Guerrero, Juan Jose; Llaberia Griño, Jose M.; Llosa Espuny, Jose Francisco; Villavieja Prados, Carlos; Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel; Ramirez Bellido, Alejandro; Morancho Llena, Enrique; Fernandez Jimenez, Agustin; Pajuelo González, Manuel Alejandro; Olive Duran, Angel; Sanchez Carracedo, Fermin; Moreto Planas, Miquel; Verdu Mula, Javier; Abella Ferrer, Jaume; Valero Cortes, Mateo
    Participation in a competitive project

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    OpenMP extensions for FPGA Accelerators  Open access

     Cabrera, Daniel; Martorell Bofill, Xavier; Gaydadjiev, Georgi; Ayguade Parra, Eduard; Jimenez Gonzalez, Daniel
    International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
    Presentation's date: 2009-07-20
    Presentation of work at congresses

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    Reconfigurable computing is one of the paths to explore towards low-power supercomputing. However, programming these reconfigurable devices is not an easy task and still requires significant research and development efforts to make it really productive. In addition, the use of these devices as accelerators in multicore, SMPs and ccNUMA architectures adds an additional level of programming complexity in order to specify the offloading of tasks to reconfigurable devices and the interoperability with current shared-memory programming paradigms such as OpenMP. This paper presents extensions to OpenMP 3.0 that try to address this second challenge and an implementation in a prototype runtime system. With these extensions the programmer can easily express the offloading of an already existing reconfigurable binary code (bitstream) hiding all the complexities related with device configuration, bitstream loading, data arrangement and movement to the device memory. Our current prototype implementation targets the SGI Altix systems with RASC blades (based on the Virtex 4 FPGA). We analyze the overheads introduced in this implementation and propose a hybrid host/device operational mode to hide some of these overheads, significantly improving the performance of the applications. A complete evaluation of the system is done with a matrix multiplication kernel, including an estimation considering different FPGA frequencies.

  • Cómo mejorar el feedback mediante una herramienta de corrección automática

     Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel; Lopez Alvarez, David; Alonso López, Javier; Tous Liesa, Ruben; Parcerisa Bundó, Joan Manuel; Barlet Ros, Pere; Fernandez Barta, Montserrat; Tubella Murgadas, Jordi; Pérez, Christian
    Jornades de Docència del Departament d'Arquitectura de Computadors
    Presentation's date: 2008-02-15
    Presentation of work at congresses

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  • Triple ¿Feedback¿ rápido para fomentar el trabajo colaborativo en casa

     Jimenez Gonzalez, Daniel; Lopez Alvarez, David; Alvarez Martinez, Carlos; Alonso López, Javier
    Jornades de Docència del Departament d'Arquitectura de Computadors
    Presentation's date: 2008-02-14
    Presentation of work at congresses

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  • Drug design issues on the Cell BE

     Servat Gelabert, Harald; González Álvarez, Cecilia; Aguilar, Xavier; Cabrera Benitez, Daniel; Jimenez Gonzalez, Daniel
    International Conference on High Performance and Embedded Architectures and Compilers
    Presentation's date: 2008-01
    Presentation of work at congresses

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  • Work in Progress - Achieving the ABET professional Skills Using Solidarity Projects

     Alonso López, Javier; Lopez Alvarez, David; Cruz Diaz, Josep-llorenç; Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel; Fernandez Jimenez, Agustin; Sanchez Carracedo, Fermin
    Frontiers in Education Conference 2008
    Presentation's date: 2008-10
    Presentation of work at congresses

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  • Trabajo no presencial en colaboración: triple realimentación a coste razonable

     Jimenez Gonzalez, Daniel
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation's date: 2008-07-09
    Presentation of work at congresses

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  • SISA-EMU: feedback automático para ensamblador

     Jimenez Gonzalez, Daniel
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation's date: 2008-07-09
    Presentation of work at congresses

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  • Trabajo no presencial en colaboración: triple realimentación a coste razonable

     Jimenez Gonzalez, Daniel; Lopez Alvarez, David; Alvarez Martinez, Carlos; Alonso López, Javier
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation of work at congresses

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  • SISA-EMU: feedback automático para ensamblador

     Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel; Lopez Alvarez, David; Alonso López, Javier; Tous Liesa, Ruben; Parcerisa Bundó, Joan Manuel; Barlet Ros, Pere; Fernandez Barta, Montserrat; Tubella Murgadas, Jordi; Christian, Pérez
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation of work at congresses

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  • Participación en dos misiones docentes a Burkina Faso,

     Jimenez Gonzalez, Daniel; Garcia, Jordi
    Participation in a competitive project

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  • Work in Progress-Improving Feedback Using an Automatic Assessment Tool

     Jimenez Gonzalez, Daniel; Alvarez Martinez, Carlos; Lopez Alvarez, David; Parcerisa Bundó, Joan Manuel; Alonso López, Javier; Christian, Pérez; Tous Liesa, Ruben; Barlet Ros, Pere; Fernandez Barta, Montserrat; Tubella Murgadas, Jordi
    Frontiers in Education Conference 2008
    Presentation's date: 2008-10-22
    Presentation of work at congresses

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  • Como obtener triple realimentación a coste razonable mediante el trabajo no presencial en colaboración

     Jimenez Gonzalez, Daniel; Lopez Alvarez, David; Alvarez Martinez, Carlos; Alonso López, Javier
    Date: 2008-10
    Report

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  • Una herramienta automática de feedback para ensamblador

     Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel; Lopez Alvarez, David; Alonso López, Javier; Tous Liesa, Ruben; Parcerisa Bundó, Joan Manuel; Barlet Ros, Pere; Fernandez Barta, Montserrat; Tubella Murgadas, Jordi; Christian, Pérez
    Date: 2008-10
    Report

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  • Case of Study: a Molecular Dynamics Application on the Cell BE

     Jimenez Gonzalez, Daniel; Cabrera, Daniel Benítez
    Date: 2008-06
    Report

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  • Work in Progress - Benefits of Cooperative Learning in a Multidisciplinary Course

     Alvarez Martinez, Carlos; Lopez Alvarez, David; Jimenez Gonzalez, Daniel; Alonso López, Javier
    Frontiers in Education Conference 2008
    Presentation of work at congresses

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  • L'assignatura Programació Conscient de l'Arquitectura

     Fernandez Jimenez, Agustin; Jimenez Gonzalez, Daniel; Larriba Pey, Josep; Morancho Llena, Enrique; Ramirez Bellido, Alejandro
    Jornades de Docència del Departament d'Arquitectura de Computadors. 10 Anys de Jornades
    Presentation of work at congresses

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  • Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications

     Jimenez Gonzalez, Daniel; Martorell Bofill, Xavier; Ramirez Bellido, Alejandro
    2007 IEEE International Symposium on Performance Analysis of Systems And Software (ISPASS'07)
    Presentation of work at congresses

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  • Drug Design Issues on the Cell BE

     Harald, Servat; González, Cecilia Noemí; Aguilar, Xavier; Cabrera, Daniel; Jimenez Gonzalez, Daniel
    Date: 2007-07
    Report

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  • Drug Design on the Cell BroadBand Engine

     Servat Gelabert, Harald; González, Cecilia Noemí; Aguilar, Xavier; Cabrera, Daniel; Jimenez Gonzalez, Daniel
    XVIII Jornadas de Paralelismo. CEDI 2007 II Congreso Español de Informática.
    Presentation of work at congresses

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  • The Performance Analysis of Cell Broadband Engine for General Purpose Programming Models

     Jimenez Gonzalez, Daniel; Martorell Bofill, Xavier; Ramirez Bellido, Alejandro
    Date: 2006-11
    Report

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  • Parallel Mutant Reverse Sorting

     Jimenez Gonzalez, Daniel; Navarro Guerrero, Juan Jose; Larriba Pey, Josep
    Date: 2005-07
    Report

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  • Algoritmos de ordenación conscientes de la arquitectura y las características de los datos.

     Jimenez Gonzalez, Daniel
    Defense's date: 2004-07-02
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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  • Characterization of the data access behavior for TPC-C traces

     Bonilla-Lucas, R; Sachedina, A; Zuzarte, C; Plachta, P; Jimenez Gonzalez, Daniel; Larriba Pey, Josep
    2004 IEEE International Symposium on Performance Analysis of Systems And Software (ISPASS'04)
    Presentation's date: 2004-03-10
    Presentation of work at congresses

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  • CC-Radix: a Cache Conscious Sorting Based on Radix sort

     Jimenez Gonzalez, Daniel; Navarro Guerrero, Juan Jose; Larriba Pey, Josep
    Euromicro Conference on Parallel, Distributed and Network-Based Processing
    Presentation of work at congresses

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  • Case Study: Memory Conscious Parallel Sorting

     Jimenez Gonzalez, Daniel; Larriba Pey, Josep; Navarro Guerrero, Juan Jose
    Date of publication: 2003-03-31
    Book chapter

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