Secure chips are in permanent risk of attacks.
Physical attacks usually start removing part of the package and
accessing the dice by different means: laser shots, electrical or
electromagnetic probes, etc. Doing this from the backside of
the chip gives some advantages since no metal layers interfere
between the hacker and the signals of interest. The bulk silicon is
thinned from hundreds to some tens of micrometers in order to
improve the performance of the attack. In this paper a backside
polishing detector is presented that is sensitive to the thickness
of the bulk silicon existing below the transistors, a numerical
signature is generated which is related to this. The detector
implements built-in self-surveillance techniques which protect it
from being tampered.
Arumi, D.; Rodriguez, R.; Figueras, J. IEEE transactions on very large scale integration (VLSI) systems Vol. 24, num. 5, p. 1739-1748 DOI: 10.1109/TVLSI.2015.2477103 Date of publication: 2015-09-24 Journal article
Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies.
Arumi, D.; Rodriguez, R.; Figueras, J. IEEE transactions on very large scale integration (VLSI) systems Vol. PP, num. 99, p. 31-36 DOI: 10.1109/TVLSI.2015.2448594 Date of publication: 2015-08-07 Journal article
Through-silicon vias (TSVs) are critical elements in 3-D integrated circuits susceptible to defects during fabrication and lifetime. It is desirable to detect defective TSVs in the early steps of the fabrication process to prevent stacking yield loss. Thus, the development of effective prebond testing techniques becomes of great importance. In this direction, recent research effort has been devoted to the development of two main prebond techniques: 1) prebond probing and 2) built-in self-test (BIST) techniques. The prebond probing poses economic and technological challenges, whereas current BIST proposals have disadvantages for certain solutions. Hence, there is still a need for an effective methodology in terms of fault coverage, area overhead, and test time. This paper proposes a BIST technique based on a simple unbalanced circuit comparing the behavior of two TSVs. Electrical simulation results show the viability of the proposal to detect weak defects, i.e., resistive opens and resistive bridges, adding reasonable area overhead in a short-test application time. Furthermore, an experimental design is built on a 65-nm technology, where resistive open defects are intentionally injected. Automated test equipment measurements confirm the simulation results
The relentless decrease in feature size and the increase of density requirements in Integrated Circuit (IC)
manufacturing arise new challenges that must be overcome. One of the most promising alternatives is three-dimensional integrated circuits (3D ICs). Several possibilities have been presented, but one of the clearest options is based on the use of Though-Silicon Vias (TSV) connections. The benefits and disadvantages that TSV inclusion adds to design need further studies. The implementation of these vertical vias can affect the general performance of circuit and thus changing verification strategies or testing processes. In this paper, the electrical effect of open defects affecting TSVs in a 3D SRAM module is presented. Analytical expressions are presented to provide
designers a tool to improve circuit features and help them in the analysis of how TSV implementation can affect a SRAM array design
Test structures are key elements to characterise and identify the main contributors to yield loss in wiring structures. Among such monitors, comb-meander-comb structures have been widely used owing to their simplicity and reduced number of pads. With continuous scaling of dimensions and use of copper in interconnections, open defects has arisen as the most common defect affecting the interconnection, focusing thus on an important part of the research effort. In fact, present electrical methodologies are able to detect, localise and predict the resistance of weak (resistive) opens. However, such methodologies are not able to locate full opens. This lack of information may be useful for faster ramp-up and yield improvement, among others. In this context, a simple electrical methodology to predict the location of full opens in comb-meander-comb structures is presented. Experimental measurements carried out in a 65 nm technology die corroborate the feasibility of the approach.
Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during their life time. Typical defects are microvoids, underfilling, misalignement,
pinholes in the oxide or misalignments during bonding in such a way that resistive opens become a frequent failure mechanism affecting TSVs. Although there is considerable research effort dedicated to improve TSVs testing, no much attention has been paid to weak defects, especially to weak open defects (resistive opens) causing small delays. In this work, a testing strategy is proposed to detect small delay defects by means of a post-bond oscillation test. Variations in the Duty Cycle of transmitted signals after unbalanced logic gates are shown to detect weak open defects in TSVs. HSPICE simulations including process parameter variations show the effectiveness of the method in the detection of weak open defects above 1 kO.
Present techniques for attacking secure devices include chip backside reverse engineering. In this presentation a detector sensitive to the removal of silicon backside material is presented. It is based on the side effect of the through silicon bias used for high bandwith communication through silicon die in digital chips.
Arumi, D.; Rodriguez, R.; Figueras, J.; Eichenberger, S.; Hora, C.; Kruseman, B. IEEE transactions on computer-aided design of integrated circuits and systems Vol. 32, num. 2, p. 301-312 DOI: 10.1109/TCAD.2012.2228269 Date of publication: 2013-02 Journal article
Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects
built-in self test integrated circuit testing three-dimensional integrated circuits
La invención presenta un sistema autotest integrado para la detección de defectos en TSVs (Through Silicon Vias o vías a través de silicio) durante la fase pre-bond, durante la cual solo uno de los terminales de la TSV es accesible. En ausencia de un defecto, el sistema evoluciona siempre hacia un mismo estado predefinido. En presencia de un defecto, el sistema evoluciona hacia otro estado diferente del establecido en ausencia de defecto. Esta invención permite a su vez que la misma estructura se utilice para la reconfiguración del circuito al final del proceso de fabricación si el resultado del test determina la presencia de una TSV defectuosa.
Arumi, D.; Rodriguez, R.; Figueras, J.; Eichenberger, S.; Hora, C.; Kruseman, B. IEEE transactions on very large scale integration (VLSI) systems Vol. 19, num. 12, p. 2209-2220 DOI: 10.1109/TVLSI.2010.2077315 Date of publication: 2011-12 Journal article
An Interconnect full open defect breaks the connection
between the driver and the gate terminals of downstream transistors,
generating a floating line. The behavior of floating lines is
known to depend on several factors, namely parasitic capacitances
to neighboring structures, transistor capacitances of downstream
gate(s) and trapped charges. For nanometer CMOS technologies,
the reduction of oxide thickness leads to a significant increase in
gate tunneling leakage. This new phenomenon influences the behavior
of circuits with interconnect full open defects. Floating lines
can no longer be considered electrically isolated and are subjected
to transient evolutions, reaching a steady state determined by the
technology, downstream interconnect and gate(s) topology. The occurrence
of such defects and the impact of gate tunneling leakage
are expected to increase in the future. In this work, interconnect
full open defects affecting nanometer CMOS technologies are analyzed
and the defective logic response of downstream gates after
reaching the steady state is predicted. Experimental evidence of
this behavior is presented for circuits belonging to a 180 nm and
a 65 nm CMOS technologies. Technology trends show that the impact
of gate leakage currents is expected to increase in future technologies.
Arumi, D.; Rodriguez, R.; Figueras, J.; Eichenberger, S.; Hora, C.; Kruseman, B. IEEE transactions on computer-aided design of integrated circuits and systems Vol. 30, num. 12, p. 1911-1922 DOI: 10.1109/TCAD.2011.2165071 Date of publication: 2011-12 Journal article
Rodriguez, R.; Arumi, D.; Manich, S.; Figueras, J.; Stefano Di Carlo; Paolo Prinetto; Scionti, A. International Conference on Advances in System Testing and Validation Lifecycle p. 81-86 DOI: 10.1109/VALID.2010.19 Presentation's date: 2010-08-24 Presentation of work at congresses
The development of accurate diagnosis
methodologies is important to solve process problems and achieve fast yield improvement. As open defects are common in CMOS
technologies, accurate diagnosis of open defects becomes a key factor. Widely used interconnect full open diagnosis procedures
are based on the assumption that neighbouring lines determine the voltage of the defective line. However, this assumption
decreases the diagnosis efficiency for opens in interconnect lines with fan-out, when the influence of transistor capacitances
becomes important. This work presents a diagnosis methodology for interconnect full open defects where the impact of transistor
parasitic capacitances is included. The methodology is able to properly diagnose interconnect opens with fan-out even in the
presence of Byzantine behaviour. Diagnosis results for real defective devices from different technology nodes are presented.
A technique for extracting the electrical and topological
parameters of open defects in process monitor lines is
presented. The procedure is based on frequency-domain measurements
performed at both end points of the line. The location
as well as the resistive value of the open defect are derived from
attenuation and phase shift measurements. The characteristic
defect-free impedance of the line and its propagation constant
are considered to be unknowns, and their values are also derived
from the above measurements. In this way, the impact of process
parameter variations on the proposed model is diminished. The
experimental setup required to perform the characterization
measurements and a simple graphical procedure to determine the
defect and line parameters are presented. Experimental results
show a good agreement between the predicted location of the open
and its real location, found by optical beam induced resistance
change inspection. Errors smaller than 2% of the total length of
the line have been observed in the experiments.
Les dimensions dels transistors disminueixen per a cada nova tecnologia CMOS. Aquest alt nivell d'integració complica el procés de fabricació dels circuits integrats, apareixent nous mecanismes de fallada. En aquest sentit, els mètodes de diagnosi actuals no són capaços d'assumir els nous reptes que sorgeixen per a les tecnologies nanomètriques. A més, la inspecció física de fallades (Failure Analysis) no es pot aplicar des d'un bon començament, ja que els costos de la seva utilització són massa alts. Per aquesta raó, conèixer el comportament dels defectes i dels seus mecanismes de fallada és imprescindible per al desenvolupament de noves metodologies de diagnosi que puguin superar aquests nous reptes. En aquest context, aquesta tesi presenta l'anàlisi dels mecanismes de fallada i proposa noves metodologies de diagnosi per millorar la localització de ponts (bridge) i oberts (open). Per a la diagnosi de ponts, alguns treballs s'han beneficiat de la informació obtinguda durant el test de corrent (IDDQ). No obstant no han tingut en compte l'impacte del corrent de dowsntream. Per aquesta raó, en aquesta tesi s'analitza l'impacte d'aquest corrent degut als ponts i la seva dependència amb la tensió d'alimentació (VDD). A més, es presenta una nova metodologia de diagnosi basada en els múltiples nivells de corrent. Aquesta tècnica considera els corrents generats per les diferents xarxes connectades pel pont. Aquesta metodologia s'ha aplicat amb èxit a un conjunt de xips defectuosos de tecnologies de 0.18 µm i 90 nm. Com alternativa a les tècniques basades en corrent, els shmoo plots també poden ser útils per a la diagnosi. Tradicionalment s'ha considerat que valors baixos de VDD són més apropiats per a la detecció de ponts. Tanmateix es demostra en aquesta tesi que en presència de ponts connectant xarxes equilibrades, valors alts de VDD són fins i tot més apropiats que tensions baixes, amb la conseqüent implicació que això té per a la diagnosi. En relació als oberts, s'ha dissenyat i fabricat un xip amb la inclusió intencionada d'oberts complets (full opens) i oberts resistius. Experiments fets amb els xips demostren l'impacte de les capacitats d'acoblament de les línies veïnes. A més, pels oberts resistius s'ha comprovat la influència de l'efecte història i de la localització de l'obert en el retard. Tradicionalment s'ha considerat que el retard màxim s'obté quan un obert resistiu es troba al principi de la línia. No obstant això no es pot generalitzar a oberts poc resistius, ja que en aquests casos es demostra que el màxim retard s'obté per a una localització intermèdia. A partir dels resultats experimentals obtinguts amb el xip, s'ha desenvolupat una nova metodologia per a la diagnosi d'oberts complets a les línies d'interconnexió. Aquest mètode divideix la línia en diferents segments segons la informació de layout de la pròpia línia. Aleshores coneixent els valors de les línies veïnes, es prediu la tensió del node flotant, la qual es compara amb el resultat experimental obtingut a la màquina de test. Aquest mètode s'ha aplicat amb èxit a un seguit de xips defectuosos pertanyents a una tecnologia de 0.18 µm. Finalment, s'ha analitzat l'impacte que tenen els corrents de túnel a través del terminal de porta en presència d'un obert complet. Com les dimensions disminueixen per a cada nova tecnologia, l'òxid de porta és suficientment prim com per generar corrents de túnel que influencien el node flotant. Aquests corrents generen una evolució temporal al node flotant fins fer-lo arribar a un estat quiescent, el qual depèn de la tecnologia. Es comprova que aquestes evolucions temporals són de l'ordre de segons per a una tecnologia de 0.18 µm. Tanmateix les simulacions demostren que aquests temps disminueixen fins a uns quants µs per a tecnologies futures. Degut a l'impacte dels corrents de túnel, un seguit d'oberts complets s'han diagnosticat en xips de 0.18 µm.
Transistor dimensions are scaled down for every new CMOS technology. Such high level of integration has increased the complexity of the Integrated Circuits (ICs) manufacturing process, arising new complex failure mechanisms. However, present diagnosis methodologies cannot afford the challenges arisen for future technologies. Furthermore, physical failure analysis, although indispensable, is not feasible on its own, since it requires high cost equipment, tools and qualified personnel. For this reason, a detailed understanding and knowledge of defect behaviours is a key factor for the development of improved diagnosed methodologies to overcome the challenges of nanometer technologies. In this context, this thesis presents the analysis of existing and new failure mechanisms and proposed new diagnosis methodologies to improve the diagnosis of faults, focused on bridging and open faults. IDDQ is a well known technique for the diagnosis of bridging faults. However, previous works have not considered the impact of the downstream current for the diagnosis of such faults. In this thesis, the impact and the dependence of the downstream current with the power supply voltage (VDD) is analyzed and experimentally measured. Furthermore, a multiple level IDDQ based diagnosis technique is presented. This method takes benefit from the currents generated by the different network excitations. This technique is successfully applied to real defective devices from 0.18 µm and 90 nm technologies. As an alternative to current based techniques, shmoo plots can be also useful for diagnosis purposes. Low voltage has been traditionally considered as an advantageous condition for the detection of bridging faults. However, it is demonstrated that in presence of bridges connecting balanced n- and p-networks, high VDD values are also advantageous for the detection of bridges, which has its direct translation into diagnosis application. Experimental evidence of this fact is presented. Related to open faults, an experimental chip has been designed and fabricated in a 0.35 µm technology, where full and resistive open defects have been intentionally added. Different experiments have been carried out so that the impact of the neighbouring coupling capacitances has been quantified. Furthermore, for resistive opens, experiments have demonstrated the influence of the history effect and the location of the defect on the delay. Traditionally, it has been reported that the highest delay is obtained when the resistive open is located at the beginning of the net. Nevertheless, this thesis demonstrates that this is not true for low resistive open, since the highest delay is obtained for an intermediate location. Experimental measurements prove this behaviour. Derived from the results obtained with the fabricated chip, a new methodology for the diagnosis of interconnect full open defects is developed. The FOS (Full Open Segment) method divides the interconnect line into different segments based on the topology of the faulty line. Knowing the logic state of the neighbouring lines, the floating net voltage is predicted and compared with the experimental results obtained on the tester. This method has been successfully applied to a set of 0.18 µm defective devices. Finally, the impact of the gate tunnelling leakage currents on the behaviour of full open defects has also been analyzed. As technology dimensions are scaled down, the oxide thickness is thin enough so that the gate tunnelling leakage currents influence the behaviour of floating lines. They cause transient evolutions on the floating node until reaching the steady state, which is technology dependent. It is experimentally demonstrated that these evolutions are in the order of seconds for a 0.18µm technology. However, for future technologies, simulations show that the evolutions decrease down to a few µs. Based on this factor, some full open faults present in 0.18 µm technology devices are diagnosed.
Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents
impact the behaviour of these lines, which cannot be considered electrically isolated anymore. The voltage of the floating node is
determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented.
Electronics Letter of the Month
Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered
electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented.
Rodriguez, R.; Arumi, D.; Figueras, J.; Eichenberger, S.; Hora, C.; Kruseman, B.; Lousberg, M.; Majhi, A.K. IEEE VLSI Test Symposium p. 1-6 DOI: 10.1109/TEST.2008.4700575 Presentation's date: 2007-05-07 Presentation of work at congresses
Best Paper Award al millor article del congrés IEEE VLSI Test Symposium 2007
A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the
division of the defective line into a number of segments. The selected group of segments is derived from the topology of the
line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the
line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current
consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to
discriminate between different locations of the full open defect.
Rodriguez, R.; Arumi, D.; Figueras, J.; Einchenberger, S.; Hora, C.; Kruseman, B.; Lousberg, M.; Majhi, A. IEEE VLSI Test Symposium p. 145-150 Presentation's date: 2007-05-07 Presentation of work at congresses