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  • Diagnosis of interconnect full open defects in the presence of gate leakage currents

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2013-02
    Journal article

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  • BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    IEEE European Test Symposium
    Presentation of work at congresses

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    Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects

    Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects

    built-in self test integrated circuit testing three-dimensional integrated circuits

  • Backside polishing detector

     Manich Bou, Salvador; Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Sigl, Georg; Mujal, Jordi
    Workshop on Trustworthy Manufacturing and Utilization of Secure Devices
    Presentation's date: 2013-12-13
    Presentation of work at congresses

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    Present techniques for attacking secure devices include chip backside reverse engineering. In this presentation a detector sensitive to the removal of silicon backside material is presented. It is based on the side effect of the through silicon bias used for high bandwith communication through silicon die in digital chips.

  • Adaptive self test of defective TSVs

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2012-11-30
    Presentation of work at congresses

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  • Circuito de autotest integrado de TSVs

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date of request: 2012-10-09
    Invention patent

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    La invención presenta un sistema autotest integrado para la detección de defectos en TSVs (Through Silicon Vias o vías a través de silicio) durante la fase pre-bond, durante la cual solo uno de los terminales de la TSV es accesible. En ausencia de un defecto, el sistema evoluciona siempre hacia un mismo estado predefinido. En presencia de un defecto, el sistema evoluciona hacia otro estado diferente del establecido en ausencia de defecto. Esta invención permite a su vez que la misma estructura se utilice para la reconfiguración del circuito al final del proceso de fabricación si el resultado del test determina la presencia de una TSV defectuosa.

  • Access to the full text
    Gate leakage impact on full open defects in interconnect lines  Open access

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram
    IEEE transactions on very large scale integration (VLSI) systems
    Date of publication: 2011-12
    Journal article

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    An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage. This new phenomenon influences the behavior of circuits with interconnect full open defects. Floating lines can no longer be considered electrically isolated and are subjected to transient evolutions, reaching a steady state determined by the technology, downstream interconnect and gate(s) topology. The occurrence of such defects and the impact of gate tunneling leakage are expected to increase in the future. In this work, interconnect full open defects affecting nanometer CMOS technologies are analyzed and the defective logic response of downstream gates after reaching the steady state is predicted. Experimental evidence of this behavior is presented for circuits belonging to a 180 nm and a 65 nm CMOS technologies. Technology trends show that the impact of gate leakage currents is expected to increase in future technologies.

    Postprint (author's final draft)

  • Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, Camelia; Kruseman, Bram
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2011-12
    Journal article

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  • Impacto de la variabilidad en las estrategias de test y diagnóstico de circuitos micro/nanoelectrónicos

     Balado Suarez, Luz Maria; Sanahuja Moliner, Ricard; Lupon Roses, Emilio Jose; Rius Vazquez, Jose; Rodríguez Montañés, Rosa; Manich Bou, Salvador; Vatajelu, Elena Ioana; Arumi Delgado, Daniel; Figueras Pamies, Juan
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  • 8T SRAM Cell with Open Defects under Voltage and Timing Variations

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Castillo Muñoz, Raul
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2011-11-16
    Presentation of work at congresses

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    Localization and Electrical Characterization of Interconnect Open Defects  Open access

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Beverloo, Willem; de Vries, Dirk K.; Eichenberger, Stefan; Volf, Paul A. J.
    IEEE transactions on semiconductor manufacturing
    Date of publication: 2010-02
    Journal article

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    A technique for extracting the electrical and topological parameters of open defects in process monitor lines is presented. The procedure is based on frequency-domain measurements performed at both end points of the line. The location as well as the resistive value of the open defect are derived from attenuation and phase shift measurements. The characteristic defect-free impedance of the line and its propagation constant are considered to be unknowns, and their values are also derived from the above measurements. In this way, the impact of process parameter variations on the proposed model is diminished. The experimental setup required to perform the characterization measurements and a simple graphical procedure to determine the defect and line parameters are presented. Experimental results show a good agreement between the predicted location of the open and its real location, found by optical beam induced resistance change inspection. Errors smaller than 2% of the total length of the line have been observed in the experiments.

  • Simulations of interconnect open faults

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2010-11
    Report

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  • Detectability study of single via opens in a 90nm technology design

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2010-10
    Report

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  • Diagnosis of full open defects in interconnect lines with fan-out

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2010-11
    Report

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  • Defective Behaviour of an 8T SRAM Cell with Open Defects

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Manich Bou, Salvador; Figueras Pamies, Juan; Di Carlo, Stefano; Prinetto, Paolo; Scionti, Alberto
    International Conference on Advances in System Testing and Validation Lifecycle
    Presentation's date: 2010-08-24
    Presentation of work at congresses

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  • Diagnosis of full open defects in interconnect lines with fan-out

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram
    IEEE European Test Symposium
    Presentation's date: 2010-05-27
    Presentation of work at congresses

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  • Delay caused by resistive opens in interconnecting lines

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras, J
    Integration. The VLSI journal
    Date of publication: 2009-06
    Journal article

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  • Models for Bridging Defects

     Renovell, Michel; Azais, Florence; Figueras Pamies, Juan; Rodríguez Montañés, Rosa; Arumi Delgado, Daniel
    Date of publication: 2009-11-01
    Book chapter

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  • Open defects in nanometer technologies

     Figueras Pamies, Juan; Rodríguez Montañés, Rosa; Arumi Delgado, Daniel
    Date of publication: 2009-11-01
    Book chapter

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  • Qualitat en Electrònica: Disseny de Baix Consum, Test, Verificació i Tolerància a Fallades

     Figueras Pamies, Juan; Carrasco Lopez, Juan Antonio; Lupon Roses, Emilio Jose; Manich Bou, Salvador; Rodríguez Montañés, Rosa; Rius Vazquez, Jose; Balado Suarez, Luz Maria; Ferre Fabregas, Antoni; Suñe Socias, Victor Manuel; Arumi Delgado, Daniel; Sanahuja Moliner, Ricard
    Participation in a competitive project

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  • HI2008-0041 Acción integrada de investigación científica y tecnológica entre España e Italia

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Manich Bou, Salvador
    Participation in a competitive project

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  • Diagnosis of Full Open Defects in Interconnect Lines with Large Fan-out

     Arumi Delgado, Daniel; Rodríguez-Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2009-11-18
    Presentation of work at congresses

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  • Experimental Characterization of CMOS Interconnect Open Defects

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2008-01
    Journal article

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  • VTS07 Best Paper Award

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Rodríguez-Montañés, R; Eichenberger, Stefan; Hora, C; Kruseman, Bram; Lousberg, M; Majhi, A K
    Award or recognition

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  • Full open defects under tunnelling leakage current in nanometric CMOS

     Arumi Delgado, Daniel; Rodríguez-Montañés, R; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C; Kruseman, Bram
    IEEE VLSI Test Symposium
    Presentation's date: 2008-04-28
    Presentation of work at congresses

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  • Impact of Gate Leakage Currents on Full Open Defects in SRAM Cells

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2008-11-12
    Presentation of work at congresses

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  • Time-dependent behaviour of full open defects in interconnecting lines

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C; Kruseman, Bram
    INTERNATIONAL TEST CONFERENCE
    Presentation's date: 2008-10-29
    Presentation of work at congresses

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  • Enhancement of defect diagnosis based on the analysis of CMOS DUT behaviour  Open access

     Arumi Delgado, Daniel
    Defense's date: 2008-07-11
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    Les dimensions dels transistors disminueixen per a cada nova tecnologia CMOS. Aquest alt nivell d'integració complica el procés de fabricació dels circuits integrats, apareixent nous mecanismes de fallada. En aquest sentit, els mètodes de diagnosi actuals no són capaços d'assumir els nous reptes que sorgeixen per a les tecnologies nanomètriques. A més, la inspecció física de fallades (Failure Analysis) no es pot aplicar des d'un bon començament, ja que els costos de la seva utilització són massa alts. Per aquesta raó, conèixer el comportament dels defectes i dels seus mecanismes de fallada és imprescindible per al desenvolupament de noves metodologies de diagnosi que puguin superar aquests nous reptes. En aquest context, aquesta tesi presenta l'anàlisi dels mecanismes de fallada i proposa noves metodologies de diagnosi per millorar la localització de ponts (bridge) i oberts (open). Per a la diagnosi de ponts, alguns treballs s'han beneficiat de la informació obtinguda durant el test de corrent (IDDQ). No obstant no han tingut en compte l'impacte del corrent de dowsntream. Per aquesta raó, en aquesta tesi s'analitza l'impacte d'aquest corrent degut als ponts i la seva dependència amb la tensió d'alimentació (VDD). A més, es presenta una nova metodologia de diagnosi basada en els múltiples nivells de corrent. Aquesta tècnica considera els corrents generats per les diferents xarxes connectades pel pont. Aquesta metodologia s'ha aplicat amb èxit a un conjunt de xips defectuosos de tecnologies de 0.18 µm i 90 nm.Com alternativa a les tècniques basades en corrent, els shmoo plots també poden ser útils per a la diagnosi. Tradicionalment s'ha considerat que valors baixos de VDD són més apropiats per a la detecció de ponts. Tanmateix es demostra en aquesta tesi que en presència de ponts connectant xarxes equilibrades, valors alts de VDD són fins i tot més apropiats que tensions baixes, amb la conseqüent implicació que això té per a la diagnosi.En relació als oberts, s'ha dissenyat i fabricat un xip amb la inclusió intencionada d'oberts complets (full opens) i oberts resistius. Experiments fets amb els xips demostren l'impacte de les capacitats d'acoblament de les línies veïnes. A més, pels oberts resistius s'ha comprovat la influència de l'efecte història i de la localització de l'obert en el retard. Tradicionalment s'ha considerat que el retard màxim s'obté quan un obert resistiu es troba al principi de la línia. No obstant això no es pot generalitzar a oberts poc resistius, ja que en aquests casos es demostra que el màxim retard s'obté per a una localització intermèdia. A partir dels resultats experimentals obtinguts amb el xip, s'ha desenvolupat una nova metodologia per a la diagnosi d'oberts complets a les línies d'interconnexió. Aquest mètode divideix la línia en diferents segments segons la informació de layout de la pròpia línia. Aleshores coneixent els valors de les línies veïnes, es prediu la tensió del node flotant, la qual es compara amb el resultat experimental obtingut a la màquina de test. Aquest mètode s'ha aplicat amb èxit a un seguit de xips defectuosos pertanyents a una tecnologia de 0.18 µm.Finalment, s'ha analitzat l'impacte que tenen els corrents de túnel a través del terminal de porta en presència d'un obert complet. Com les dimensions disminueixen per a cada nova tecnologia, l'òxid de porta és suficientment prim com per generar corrents de túnel que influencien el node flotant. Aquests corrents generen una evolució temporal al node flotant fins fer-lo arribar a un estat quiescent, el qual depèn de la tecnologia. Es comprova que aquestes evolucions temporals són de l'ordre de segons per a una tecnologia de 0.18 µm. Tanmateix les simulacions demostren que aquests temps disminueixen fins a uns quants µs per a tecnologies futures. Degut a l'impacte dels corrents de túnel, un seguit d'oberts complets s'han diagnosticat en xips de 0.18 µm.

    Transistor dimensions are scaled down for every new CMOS technology. Such high level of integration has increased the complexity of the Integrated Circuits (ICs) manufacturing process, arising new complex failure mechanisms. However, present diagnosis methodologies cannot afford the challenges arisen for future technologies. Furthermore, physical failure analysis, although indispensable, is not feasible on its own, since it requires high cost equipment, tools and qualified personnel. For this reason, a detailed understanding and knowledge of defect behaviours is a key factor for the development of improved diagnosed methodologies to overcome the challenges of nanometer technologies. In this context, this thesis presents the analysis of existing and new failure mechanisms and proposed new diagnosis methodologies to improve the diagnosis of faults, focused on bridging and open faults.IDDQ is a well known technique for the diagnosis of bridging faults. However, previous works have not considered the impact of the downstream current for the diagnosis of such faults. In this thesis, the impact and the dependence of the downstream current with the power supply voltage (VDD) is analyzed and experimentally measured. Furthermore, a multiple level IDDQ based diagnosis technique is presented. This method takes benefit from the currents generated by the different network excitations. This technique is successfully applied to real defective devices from 0.18 µm and 90 nm technologies.As an alternative to current based techniques, shmoo plots can be also useful for diagnosis purposes. Low voltage has been traditionally considered as an advantageous condition for the detection of bridging faults. However, it is demonstrated that in presence of bridges connecting balanced n- and p-networks, high VDD values are also advantageous for the detection of bridges, which has its direct translation into diagnosis application. Experimental evidence of this fact is presented.Related to open faults, an experimental chip has been designed and fabricated in a 0.35 µm technology, where full and resistive open defects have been intentionally added. Different experiments have been carried out so that the impact of the neighbouring coupling capacitances has been quantified. Furthermore, for resistive opens, experiments have demonstrated the influence of the history effect and the location of the defect on the delay. Traditionally, it has been reported that the highest delay is obtained when the resistive open is located at the beginning of the net. Nevertheless, this thesis demonstrates that this is not true for low resistive open, since the highest delay is obtained for an intermediate location. Experimental measurements prove this behaviour.Derived from the results obtained with the fabricated chip, a new methodology for the diagnosis of interconnect full open defects is developed. The FOS (Full Open Segment) method divides the interconnect line into different segments based on the topology of the faulty line. Knowing the logic state of the neighbouring lines, the floating net voltage is predicted and compared with the experimental results obtained on the tester. This method has been successfully applied to a set of 0.18 µm defective devices. Finally, the impact of the gate tunnelling leakage currents on the behaviour of full open defects has also been analyzed. As technology dimensions are scaled down, the oxide thickness is thin enough so that the gate tunnelling leakage currents influence the behaviour of floating lines. They cause transient evolutions on the floating node until reaching the steady state, which is technology dependent. It is experimentally demonstrated that these evolutions are in the order of seconds for a 0.18µm technology. However, for future technologies, simulations show that the evolutions decrease down to a few µs. Based on this factor, some full open faults present in 0.18 µm technology devices are diagnosed.

  • IDDQ-based diagnosis at very low voltage (VLV) for bridging defects

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram; Lousberg, M.
    Electronics Letters
    Date of publication: 2007-03
    Journal article

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    Impact of gate tunnelling leakage on CMOS circuits with full open defects  Open access  awarded activity

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Eichenberger, S.; Hora, Camelia; Kruseman, B.
    Electronics Letters
    Date of publication: 2007-10
    Journal article

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    Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented.

    Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented.

    Electronics Letter of the Month

  • TEC2007-66672 DIAGNOSTICO EN TECNOLOGIAS CMOS NANOMETRICAS: MEJORA DEL RENDIMIENTO

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Lupon Roses, Emilio Jose; Manich Bou, Salvador; Rius Vazquez, Jose; Balado Suarez, Luz Maria
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  • Letter of the Month

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Rodríguez-Montañés, R; Eichenberger, Stefan; Hora, C; Kruseman, Bram
    Award or recognition

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  • Process-variability aware delay fault testing of ·VT and weak-open defects

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Pineda de Gyvez, José; Gronthoud, G
    The Eighth IEEE European Test Workshop
    Presentation's date: 2007-05-27
    Presentation of work at congresses

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  • Diagnosis of Bridging Defects Based On Current Signatures at Low Power Supply Voltages

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Einchenberger, S; Hora, C; Kruseman, Bram; Lousberg, M; Majhi, A K
    IEEE VLSI Test Symposium
    Presentation's date: 2007-05-07
    Presentation of work at congresses

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    Diagnosis of full open defects in interconnecting lines  Open access

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, Camelia; Kruseman, Bram; Lousberg, M.; Majhi, A.K.
    IEEE VLSI Test Symposium
    Presentation's date: 2007-05-07
    Presentation of work at congresses

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    A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.

    Best Paper Award al millor article del congrés IEEE VLSI Test Symposium 2007

  • Impact of Gate Tunnelling Leakage on CMOS Circuits with Full Open Defects

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2007-11-22
    Presentation of work at congresses

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  • Effectiveness of very low voltage testing of bridging defects

     Rodriguez-Montanes, R; Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan
    Electronics Letters
    Date of publication: 2006-09
    Journal article

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  • Diagnosis of bridging defects

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2006-07-03
    Report

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  • Full open segment model in interconnecting lines

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2006-09-01
    Report

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  • Classification of defective Veqtor4 devices under different stress test conditions

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2006-05-02
    Report

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  • Experimental Characterization of CMOS Interconnect Open Defects

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2006-11-22
    Presentation of work at congresses

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  • Defective Behaviours of Resistive Opens in Interconnect Lines

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    10th European Test Symposium
    Presentation's date: 2005-05-23
    Presentation of work at congresses

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  • TEC2004-02625 AUTOTEST Y DIAGNOSTICO DE CIRCUITOS Y SISTEMAS INTEGRADOS HETEROGENEOS EN TECNOLOGIAS CMOS NANOMETRICAS

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Lupon Roses, Emilio Jose
    Participation in a competitive project

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  • Mixers under Vt Mismatch Defects: Detectability by Constellation Plots

     Arumi Delgado, Daniel
    Ninth European Test Symposium
    Presentation's date: 2004-05-25
    Presentation of work at congresses

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  • Testing of RF Systems by Zoning the Constellation Diagram

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation of work at congresses

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