Carretero, J.S.; Abella, J.; Vera, J.; Chaparro, P. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems p. 209-216 DOI: 10.1109/DFT.2011.32 Data de presentació: 2011 Presentació treball a congrés
Processors' design complexity increases with transistors' growing density. At the same time, market competence requires a decreasing time-to-market, and therefore, reduced validation time. Such time reduction imposes new challenges to post-Si validation strategies, processes, techniques, tools, and microprocessor hardware features. In this paper we develop a micro architectural technique to speed up the post-Si validation for one of the most complex and difficult to debug control logic pieces in the processor: the control flow recovery mechanisms used by control flow speculation, interrupts and exceptions. Our experiments show that with a small area overhead of 0.14% all post-Si bugs in this complex hardware can be detected in a timely manner, which avoids state pollution and reduces debug time.
Nowadays, multithreading is one of the most popular paradigms in microprocessor design. Several methodologies have been proposed in the literature to evaluate these processors. However, there is not a clear comparison baseline to check how accurate are the measurements obtained using any proposed methodology.
In this paper, we propose to obtain such a baseline by reexecuting all programs in the workload once and again. When every program has been reexecuted enough times, the results converge to a steady state in which all programs are fairly represented. This baseline can be easily calculated to evaluate real multithreading processors. However, obtaining the steady-state baseline in a simulation environment would require unaffordable simulation time. In order to overcome this problem, we propose to select a representative trace of each program and iterating them until the results converge. This technique makes it possible to approximate the real steady-state baseline, providing accurate baseline results in reasonable simulation time.