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  • A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness

     Cook, Henry; Moreto Planas, Miquel; Bird, Sarah L.; Dao, Khanh; Patterson, David; Asanovic, Krste
    Annual International Symposium on Computer Architecture
    Presentation of work at congresses

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    Computing workloads often contain a mix of interactive, latency-sensitive foreground applications and recurring background computations. To guarantee responsiveness, interactive and batch applications are often run on disjoint sets of resources, but this incurs additional energy, power, and capital costs. In this paper, we evaluate the potential of hardware cache partitioning mechanisms and policies to improve efficiency by allowing background applications to run simultaneously with interactive foreground applications, while avoiding degradation in interactive responsiveness. We evaluate these tradeoffs using commercial x86 multicore hardware that supports cache partitioning, and find that real hardware measurements with full applications provide different observations than past simulation-based evaluations. Co-scheduling applications without LLC partitioning leads to a 10% energy improvement and average throughput improvement of 54% compared to running tasks separately, but can result in foreground performance degradation of up to 34% with an average of 6%. With optimal static LLC partitioning, the average energy improvement increases to 12% and the average throughput improvement to 60%, while the worst case slowdown is reduced noticeably to 7% with an average slowdown of only 2%. We also evaluate a practical low-overhead dynamic algorithm to control partition sizes, and are able to realize the potential performance guarantees of the optimal static approach, while increasing background throughput by an additional 19%.

  • Task mapping in rectangular twisted tori

     Camarero Coterillo, Cristobal; Vallejo, Enrique; Martinez Fernández, Maria del Carmen; Moreto Planas, Miquel; Beivide Palacio, Ramon
    High Performance Computing Symposia
    Presentation's date: 2013-04
    Presentation of work at congresses

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    Twisted torus topologies have been proposed as an alternative to toroidal rectangular networks, improving distance parameters and providing network symmetry. However, twisting is apparently less amenable to task mapping algorithms of real life applications. In this paper we make an analytical study of different mapping and concentration techniques on 2D twisted tori that try to compensate for the twisted peripheral links. We introduce a performance model based on the network average distance and the detection of the set of links which receive the highest load. The model also considers the amount of local and global communications in the network. Our model shows that the twisted torus can improve latency and maximum throughput over rectangular torus, especially when global communications dominate over local ones and when some concentration is employed. Simulation results corroborate our synthetic model. For real applications from the NPB benchmark suite, the use of the twisted topologies with an appropriate mapping provides overall average application speedups of 2.9%, which increase to 4.9% when concentrated topologies (c = 2) are considered.

  • On the convergence of mainstream and mission-critical markets

     Girbal, Sylvain; Moreto Planas, Miquel; Grasset, Arnaud; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla, Francisco J.; Yehia, Sami
    Design Automation Conference
    Presentation of work at congresses

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    The computing market has been dominated during the last two decades by the well-known convergence of the highperformance computing market and the mobile market. In this paper we witness a new type of convergence between the mission-critical market (such as avionic or automotive) and the mainstream consumer electronics market. Such convergence is fuelled by the common needs of both markets for more reliability, support for mission-critical functionalities and the challenge of harnessing the unsustainable increases in safety margins to guarantee either correctness or timing. In this position paper, we present a description of this new convergence, as well as the main challenges and opportunities that it brings to computing industry.

  • Tessellation: Refactoring the OS around explicit resource containers with continuous adaptation

     Colmenares, Juan A.; Eads, Gage; Hofmeyry, Steven; Bird, Sarah L.; Moreto Planas, Miquel; Chou, David; Gluzman, Brian; Roman, Eric; Bartolini, Davide B.; Mor, Nitesh; Asanovic, Krste; Kubiatowicz, John D.
    Design Automation Conference
    Presentation's date: 2013-06
    Presentation of work at congresses

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    Adaptive Resource-Centric Computing (ARCC) enables a simultaneous mix of high-throughput parallel, real-time, and interactive applications through automatic discovery of the correct mix of resource assignments necessary to achieve application requirements. This approach, embodied in the Tessellation manycore operating system, distributes resources to QoS domains called cells. Tessellation separates global decisions about the allocation of resources to cells from application-specific scheduling of resources within cells. We examine the implementation of ARCC in the Tessellation OS, highlight Tessellation's ability to provide predictable performance, and investigate the performance of Tessellation services within cells.

  • The next convergence: High-performance and mission-critical markets

     Girbal, Sylvain; Moreto Planas, Miquel; Grasset, Arnaud; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier; Yehia, Sami
    High-performance and Real-time Embedded Systems
    Presentation's date: 2013-01
    Presentation of work at congresses

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    The well-known convergence of the high-performance computing and the mobile markets has been a dominating factor in the computing market during the last two decades. In this paper we witness a new type of convergence between the mission-critical market (such as avionic or automotive) and the mainstream consumer electronics market. Such convergence is fuelled by the common needs of both markets for more reliability, support for mission-critical functionalities and the challenge of harnessing the unsustainable increases in safety margins to guarantee either correctness or timing. In this position paper, we present a description of this new convergence, as well as the main challenges and opportunities that it brings to computing industry.

  • Hardware support for accurate per-task energy metering in multicore systems

     Liu, Qixiao; Moreto Planas, Miquel; Jiménez, Víctor; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortes, Mateo
    ACM transactions on architecture and code optimization
    Date of publication: 2013-12
    Journal article

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    Accurately determining the energy consumed by each task in a system will become of prominent importance in future multicore-based systems because it offers several benefits, including (i) better application energy/performance optimizations, (ii) improved energy-aware task scheduling, and (iii) energy-aware billing in data centers. Unfortunately, existing methods for energy metering in multicores fail to provide accurate energy estimates for each task when several tasks run simultaneously. This article makes a case for accurate Per-Task Energy Metering (PTEM) based on tracking the resource utilization and occupancy of each task. Different hardware implementationswith different trade-offs between energy prediction accuracy and hardware-implementation complexity are proposed. Our evaluation shows that the energy consumed in a multicore by each task can be accurately measured. For a 32-core, 2-way, simultaneous multithreaded core setup, PTEM reduces the average accuracy error from more than 12% when our hardware support is not used to less than 4% when it is used. The maximum observed error for any task in the workload we used reduces from 58% down to 9% when our hardware support is used.

  • Fair CPU time accounting in CMP+SMT processors

     Luque, Carlos; Moreto Planas, Miquel; Cazorla, Francisco J.; Valero Cortes, Mateo
    ACM transactions on architecture and code optimization
    Date of publication: 2013-01
    Journal article

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  • Optimal task assignment in multithreaded processors: a statistical approach

     Cakarevic, Vladimir; Radojkovic, Petar; Moreto Planas, Miquel; Verdu Mula, Javier; Pajuelo González, Manuel Alejandro; Cazorla, Francisco J.; Nemirovsky, Mario; Valero Cortes, Mateo
    International Conference on Architectural Support for Programming Languages and Operating Systems
    Presentation's date: 2012
    Presentation of work at congresses

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    The introduction of massively multithreaded (MMT) processors, comprised of a large number of cores with many shared resources, has made task scheduling, in particular task to hardware thread assignment, one of the most promising ways to improve system performance. However, finding an optimal task assignment for a workload running on MMT processors is an NP-complete problem. Due to the fact that the performance of the best possible task assignment is unknown, the room for improvement of current task-assignment algorithms cannot be determined. This is a major problem for the industry because it could lead to: (1)~A waste of resources if excessive effort is devoted to improving a task assignment algorithm that already provides a performance that is close to the optimal one, or (2)~significant performance loss if insufficient effort is devoted to improving poorly-performing task assignment algorithms. In this paper, we present a method based on Extreme Value Theory that allows the prediction of the performance of the optimal task assignment in MMT processors. We further show that executing a sample of several hundred or several thousand random task assignments is enough to obtain, with very high confidence, an assignment with a performance that is close to the optimal one. We validate our method with an industrial case study for a set of multithreaded network applications running on an UltraSPARC~T2 processor.

  • Characterizing thread placement in the IBM POWER7 Processor

     Manousopoulos, Stelios; Moreto Planas, Miquel; Gioiosa, Roberto; Koziris, Nectarios; Cazorla, Francisco J.
    IEEE International Symposium on Workload Characterization
    Presentation's date: 2012-11-06
    Presentation of work at congresses

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  • Kernel partitioning of streaming applications: a statistical approach to an NP-complete problem

     Radojkovic, Petar; Carpenter, Paul Matthew; Moreto Planas, Miquel; Ramirez Bellido, Alejandro; Cazorla, Francisco J.
    IEEE/ACM International Symposium on Microarchitecture
    Presentation's date: 2012-12-05
    Presentation of work at congresses

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  • Fulbright Award 2011

     Moreto Planas, Miquel
    Award or recognition

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  • CPU accounting for multicore processors

     Ruiz Luque, Jose Carlos; Moreto Planas, Miquel; Cazorla, Francisco J.; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortes, Mateo
    IEEE transactions on computers
    Date of publication: 2012-02
    Journal article

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  • Peripheral twists for torus topologies with arbitrary aspect ratio

     Vallejo Gutiérrez, Enrique; Moreto Planas, Miquel; Martínez Fernandez, Carmen; Beivide Palacio, Julio Ramon
    Jornadas de Paralelismo
    Presentation's date: 2011
    Presentation of work at congresses

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  • Simulating whole supercomputer applications

     González Garcia, Juan; Casas, Marc; Gimenez Lucas, Judit; Moreto Planas, Miquel; Ramirez Bellido, Alejandro; Labarta Mancho, Jesus Jose; Valero Cortes, Mateo
    IEEE micro
    Date of publication: 2011-06
    Journal article

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    Detailed simulations of large scale message-passing interface parallel applications are extremely time consuming and resource intensive. A new methodology that combines signal processing and data mining techniques plus a multilevel simulation reduces the simulated data by various orders of magnitude. This reduction makes possible detailed software performance analysis and accurate performance predictions in a reasonable time.

  • Dynamic cache partitioning based on the MLP of cache misses

     Moreto Planas, Miquel; Cazorla, Francisco J.; Ramirez Bellido, Alejandro; Valero Cortes, Mateo
    Lecture notes in computer science
    Date of publication: 2011
    Journal article

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  • ITCA: Inter-Task Conflict-Aware CPU accounting for CMP

     Luque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Valero Cortes, Mateo
    Jornadas de Paralelismo
    Presentation of work at congresses

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  • Load balancing using dynamic cache allocation

     Moreto Planas, Miquel; Cazorla, Francisco J.; Sakellariou, Rizos; Valero Cortes, Mateo
    ACM International Conference on Computing Frontiers
    Presentation's date: 2010-05-17
    Presentation of work at congresses

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  • Adapting cache partitioning algorithms to pseudo-LRU replacement policies

     Kedzierski, Kamil; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Valero Cortes, Mateo
    IEEE International Parallel and Distributed Processing Symposium
    Presentation's date: 2010-04
    Presentation of work at congresses

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  • Improving cache behavior in CMP architectures through cache partitioning techniques  Open access  awarded activity

     Moreto Planas, Miquel
    Defense's date: 2010-03-19
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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    The evolution of microprocessor design in the last few decades has changed significantly, moving from simple inorder single core architectures to superscalar and vector architectures in order to extract the maximum available instruction level parallelism. Executing several instructions from the same thread in parallel allows significantly improving the performance of an application. However, there is only a limited amount of parallelism available in each thread, because of data and control dependences. Furthermore, designing a high performance, single, monolithic processor has become very complex due to power and chip latencies constraints. These limitations have motivated the use of thread level parallelism (TLP) as a common strategy for improving processor performance. Multithreaded processors allow executing different threads at the same time, sharing some hardware resources. There are several flavors of multithreaded processors that exploit the TLP, such as chip multiprocessors (CMP), coarse grain multithreading, fine grain multithreading, simultaneous multithreading (SMT), and combinations of them.To improve cost and power efficiency, the computer industry has adopted multicore chips. In particular, CMP architectures have become the most common design decision (combined sometimes with multithreaded cores). Firstly, CMPs reduce design costs and average power consumption by promoting design re-use and simpler processor cores. For example, it is less complex to design a chip with many small, simple cores than a chip with fewer, larger, monolithic cores.Furthermore, simpler cores have less power hungry centralized hardware structures. Secondly, CMPs reduce costs by improving hardware resource utilization. On a multicore chip, co-scheduled threads can share costly microarchitecture resources that would otherwise be underutilized. Higher resource utilization improves aggregate performance and enables lower cost design alternatives.One of the resources that impacts most on the final performance of an application is the cache hierarchy. Caches store data recently used by the applications in order to take advantage of temporal and spatial locality of applications. Caches provide fast access to data, improving the performance of applications. Caches with low latencies have to be small, which prompts the design of a cache hierarchy organized into several levels of cache.In CMPs, the cache hierarchy is normally organized in a first level (L1) of instruction and data caches private to each core. A last level of cache (LLC) is normally shared among different cores in the processor (L2, L3 or both). Shared caches increase resource utilization and system performance. Large caches improve performance and efficiency by increasing the probability that each application can access data from a closer level of the cache hierarchy. It also allows an application to make use of the entire cache if needed.A second advantage of having a shared cache in a CMP design has to do with the cache coherency. In parallel applications, different threads share the same data and keep a local copy of this data in their cache. With multiple processors, it is possible for one processor to change the data, leaving another processor's cache with outdated data. Cache coherency protocol monitors changes to data and ensures that all processor caches have the most recent data. When the parallel application executes on the same physical chip, the cache coherency circuitry can operate at the speed of on-chip communications, rather than having to use the much slower between-chip communication, as is required with discrete processors on separate chips. These coherence protocols are simpler to design with a unified and shared level of cache onchip.Due to the advantages that multicore architectures offer, chip vendors use CMP architectures in current high performance, network, real-time and embedded systems. Several of these commercial processors have a level of the cache hierarchy shared by different cores. For example, the Sun UltraSPARC T2 has a 16-way 4MB L2 cache shared by 8 cores each one up to 8-way SMT. Other processors like the Intel Core 2 family also share up to a 12MB 24-way L2 cache. In contrast, the AMD K10 family has a private L2 cache per core and a shared L3 cache, with up to a 6MB 64-way L3 cache.As the long-term trend of increasing integration continues, the number of cores per chip is also projected to increase with each successive technology generation. Some significant studies have shown that processors with hundreds of cores per chip will appear in the market in the following years. The manycore era has already begun. Although this era provides many opportunities, it also presents many challenges. In particular, higher hardware resource sharing among concurrently executing threads can cause individual thread's performance to become unpredictable and might lead to violations of the individual applications' performance requirements. Current resource management mechanisms and policies are no longer adequate for future multicore systems.Some applications present low re-use of their data and pollute caches with data streams, such as multimedia, communications or streaming applications, or have many compulsory misses that cannot be solved by assigning more cache space to the application. Traditional eviction policies such as Least Recently Used (LRU), pseudo LRU or random are demand-driven, that is, they tend to give more space to the application that has more accesses to the cache hierarchy.When no direct control over shared resources is exercised (the last level cache in this case), it is possible that a particular thread allocates most of the shared resources, degrading other threads performance. As a consequence, high resource sharing and resource utilization can cause systems to become unstable and violate individual applications' requirements. If we want to provide a Quality of Service (QoS) to applications, we need to enhance the control over shared resources and enrich the collaboration between the OS and the architecture.In this thesis, we propose software and hardware mechanisms to improve cache sharing in CMP architectures. We make use of a holistic approach, coordinating targets of software and hardware to improve system aggregate performance and provide QoS to applications. We make use of explicit resource allocation techniques to control the shared cache in a CMP architecture, with resource allocation targets driven by hardware and software mechanisms.The main contributions of this thesis are the following:- We have characterized different single- and multithreaded applications and classified workloads with a systematic method to better understand and explain the cache sharing effects on a CMP architecture. We have made a special effort in studying previous cache partitioning techniques for CMP architectures, in order to acquire the insight to propose improved mechanisms.- In CMP architectures with out-of-order processors, cache misses can be served in parallel and share the miss penalty to access main memory. We take this fact into account to propose new cache partitioning algorithms guided by the memory-level parallelism (MLP) of each application. With these algorithms, the system performance is improved (in terms of throughput and fairness) without significantly increasing the hardware required by previous proposals.- Driving cache partition decisions with indirect indicators of performance such as misses, MLP or data re-use may lead to suboptimal cache partitions. Ideally, the appropriate metric to drive cache partitions should be the target metric to optimize, which is normally related to IPC. Thus, we have developed a hardware mechanism, OPACU, which is able to obtain at run-time accurate predictions of the performance of an application when running with different cache assignments.- Using performance predictions, we have introduced a new framework to manage shared caches in CMP architectures, FlexDCP, which allows the OS to optimize different IPC-related target metrics like throughput or fairness and provide QoS to applications. FlexDCP allows an enhanced coordination between the hardware and the software layers, which leads to improved system performance and flexibility.- Next, we have made use of performance estimations to reduce the load imbalance problem in parallel applications. We have built a run-time mechanism that detects parallel applications sensitive to cache allocation and, in these situations, the load imbalance is reduced by assigning more cache space to the slowest threads. This mechanism, helps reducing the long optimization time in terms of man-years of effort devoted to large-scale parallel applications.- Finally, we have stated the main characteristics that future multicore processors with thousands of cores should have. An enhanced coordination between the software and hardware layers has been proposed to better manage the shared resources in these architectures.

  • Twisted Torus Topologies for Enhanced Interconnection Networks

     Camara, Jose M.; Moreto Planas, Miquel; Vallejo, Enrique; Miguel Alonso, Jose; Martinez Fernandez, Maria del Carmen; Navaridas, Javier; Beivide Palacio, Julio Ramon
    IEEE transactions on parallel and distributed systems
    Date of publication: 2010-12
    Journal article

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  • ITCA: Inter-Task Conflict-Aware CPU accounting for CMPs

     Luque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortes, Mateo
    International Conference on Parallel Architectures and Compilation Techniques
    Presentation's date: 2009
    Presentation of work at congresses

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  • FlexDCP: a QoS framework for CMP architectures

     Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Ramirez Bellido, Alejandro; Sakellariou, Rizos; Valero Cortes, Mateo
    Operating systems review
    Date of publication: 2009-06
    Journal article

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  • ARQUITECTURA DE COMPUTADORS D'ALTRES PRESTACIONS (CAP)

     Jimenez Castells, Marta; Pericas Gleim, Miquel; Navarro Guerrero, Juan Jose; Llaberia Griño, Jose M.; Llosa Espuny, Jose Francisco; Villavieja Prados, Carlos; Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel; Ramirez Bellido, Alejandro; Morancho Llena, Enrique; Fernandez Jimenez, Agustin; Pajuelo González, Manuel Alejandro; Olive Duran, Angel; Sanchez Carracedo, Fermin; Moreto Planas, Miquel; Verdu Mula, Javier; Abella Ferrer, Jaume; Valero Cortes, Mateo
    Participation in a competitive project

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  • ITCA: inter-task conflict-aware CPU accounting for CMPs

     Luque, Carlos; Cazorla, Francisco J.; Gioiosa, Roberto; Buyuktosunoglu, Alper; Moreto Planas, Miquel; Valero Cortes, Mateo
    International Conference on Parallel Architectures and Compilation Techniques
    Presentation's date: 2009
    Presentation of work at congresses

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    Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism from an application. CMPs introduce complexities when accounting CPU utilization. This is due to the fact that the progress done by an application during an interval of time highly depends on the activity of the other applications it is co-scheduled with. In this paper, we identify how an inaccurate measurement of the CPU utilization affects several key aspects of the system like the application scheduling or the charging mechanism in data centers. We propose a new hardware CPU accounting mechanism to improve the accuracy when measuring the CPU utilization in CMPs and compare it with the previous accounting mechanisms. Our results show that currently known mechanisms lead to a 19% average error when it comes to CPU utilization accounting. Our proposal reduces this error to less than 1% in a modeled 4-core processor system.

  • Pseudo-LRU based cache partitioning algorithms

     Kedzierski, Kamil; Moreto Planas, Miquel
    International Conference on Parallel Architectures and Compilation Techniques
    Presentation's date: 2009
    Presentation of work at congresses

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  • CPU Accounting in CMP Processors

     Luque, C; Moreto Planas, Miquel; Cazorla, FJ; Gioiosa, R; Buyuktosunoglu, A; Valero Cortes, Mateo
    IEEE computer architecture letters
    Date of publication: 2009-01
    Journal article

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  • Multicore resource management

     Nesbit, K J; Smith, J E; Moreto Planas, Miquel; Cazorla, F J; Ramirez Bellido, Alejandro; Valero Cortes, Mateo
    IEEE micro
    Date of publication: 2008-06
    Journal article

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  • Architecture performance prediction using evolutionary artificial neural networks

     Castillo, Pedro Angel; Mora, Antonio; Merelo, Juan Julían; Laredo, Juan Luís; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Valero Cortes, Mateo; McKee, Sally
    European Workshop on Hardware Optimization Techniques
    Presentation's date: 2008
    Presentation of work at congresses

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  • MLP-aware dynamic cache partitioning

     Moreto Planas, Miquel; Cazorla, Francisco J.; Ramirez Bellido, Alejandro; Valero Cortes, Mateo
    International Conference on High Performance and Embedded Architectures and Compilers
    Presentation's date: 2008
    Presentation of work at congresses

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  • MLP - Aware Dynamic Cache Partitioning

     Moreto Planas, Miquel; Francisco, J Cazorla; Ramirez Bellido, Alejandro; Valero Cortes, Mateo
    2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC'2008)
    Presentation of work at congresses

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  • Evolutionary system for prediction and optimization of hardware architecture performance

     Castillo, Pedro Angel; Merelo, Juan Julían; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Valero Cortes, Mateo; Mora, Antonio; Laredo, Juan Luís; McKee, Sally
    IEEE Congress on Evolutionary Computation
    Presentation's date: 2008-06-01
    Presentation of work at congresses

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  • Dynamic cache partitioning based on th MLP of cache misses

     Moreto Planas, Miquel; Cazorla, Francisco J.; Valero Cortes, Mateo; Ramirez Bellido, Alejandro
    Transactions on HiPEAC
    Date of publication: 2008-06
    Journal article

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  • Modeling toroidal networks with the Gaussian integers

     Martinez, C; Beivide Palacio, Julio Ramon; Stafford, E; Moreto Planas, Miquel; Gabidulin, E M
    IEEE transactions on computers
    Date of publication: 2008-08
    Journal article

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  • Explaining Dynamic Cache Partitioning Speed Ups

     Moreto Planas, Miquel; Cazorla, F J; Ramirez Bellido, Alejandro; Valero Cortes, Mateo
    IEEE computer architecture letters
    Date of publication: 2007-01
    Journal article

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  • Online Prediction of Applications Cache Utility

     Moreto Planas, Miquel; Francisco, J Cazorla; Ramirez Bellido, Alejandro; Valero Cortes, Mateo
    2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007)
    Presentation of work at congresses

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  • Computación de Altas Prestaciones V: Arquitecturas, Compiladores, Sistemas Operativos, Herramientas y Aplicaciones

     Ramirez Bellido, Alejandro; Valero Cortes, Mateo; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Abella Ferrer, Jaume; Figueiredo Boneti, Carlos Santieri; Gioiosa, Roberto; Pajuelo González, Manuel Alejandro; Quiñones Moreno, Eduardo; Verdu Mula, Javier; Guitart Fernández, Jordi; Fernandez Jimenez, Agustin; Garcia Almiñana, Jordi; Utrera Iglesias, Gladys Miriam
    Participation in a competitive project

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  • Mixed radix Twisted Torus Interconnection Networks

     Camara, Jose M; Moreto Planas, Miquel; Vallejo, Enrique; Miguel, Jose Alonso; Navaridas, Javier; Beivide Palacio, Julio Ramon
    IEEE International Parallel and Distributed Processing Symposium
    Presentation of work at congresses

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  • MLP- Aware Dynamic Cache Partitioning

     Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Ramirez Bellido, Alejandro; Valero Cortes, Mateo
    16th International Conference on Parallel Architectures and Compilation Techniques (PACT'07)
    Presentation of work at congresses

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  • Mixed-radix Twisted Torus Interconnection Networks

     Camara, Jose M; Moreto Planas, Miquel; Vallejo, Enrique; Miguel, Jose Alonso; Navaridas, Javier; Beivide Palacio, Julio Ramon
    IEEE International Parallel and Distributed Processing Symposium
    Presentation of work at congresses

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  • Hipeac 2: European Network of Excellence on High Performance and Embedded Architecture and Compilation

     Monreal Arnal, Teresa; De Bosschere, Koen; Valero Cortes, Mateo; Moreto Planas, Miquel; Morancho Llena, Enrique; Gil Gómez, Maria Luisa
    Participation in a competitive project

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  • IPC-Aware Dynamic Cache Partitioning for CMP processors*

     Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Ramirez Bellido, Alejandro; Valero Cortes, Mateo
    Date: 2007-09
    Report

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  • Online Prediction of Throughput for Different Cache Sizes

     Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Ramirez Bellido, Alejandro; Valero Cortes, Mateo
    XVIII Jornadas de Paralelismo. CEDI 2007 II Congreso Español de Informática.
    Presentation of work at congresses

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  • A generalization of perfect Lee codes over Gaussian integers

     Martínez Fernández, Maria del Carmen; Moreto Planas, Miquel; Gabidulin, Ernst; Beivide Palacio, Julio Ramon
    IEEE International Symposium on Information Theory
    Presentation's date: 2006
    Presentation of work at congresses

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  • Scalable Computer Architecture (SARC)

     Martorell Bofill, Xavier; Valero Cortes, Mateo; Ramirez Bellido, Alejandro; Moreto Planas, Miquel; Morancho Llena, Enrique
    Participation in a competitive project

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  • Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors

     Martinez Fernandez, Maria del Carmen; Vallejo, Enrique; Cruz, Izu; Moreto Planas, Miquel; Beivide Palacio, Julio Ramon
    International journal of parallel programming
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    Journal article

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  • Hierarchical Gaussian topologies

     Moreto Planas, Miquel; Vallejo, Enrique; Valero Cortes, Mateo; Beivide Palacio, Julio Ramon
    International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
    Presentation's date: 2005
    Presentation of work at congresses

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  • Hierarchical topologies for large-scale two-level networks

     Martínez Fernández, María del Carmen; Vallejo, Enrique; Moreto Planas, Miquel; Valero Cortes, Mateo; Beivide Palacio, Julio Ramon
    Jornadas de Paralelismo
    Presentation's date: 2005-09-14
    Presentation of work at congresses

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  • Hipeac - European Network of Excellence on High-Performance Embedded Architecture and Compilation

     Valero Cortes, Mateo; Navarro Guerrero, Juan Jose; Gil Gómez, Maria Luisa; Ramirez Bellido, Alejandro; Llosa Espuny, Jose Francisco; Morancho Llena, Enrique; Canal Corretger, Ramon; Moreto Planas, Miquel
    Participation in a competitive project

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  • TIN2004-07739-C02-01 Computación de Altas Prestaciones IV: Arquitecturas, Compiladores, Sistemas Operativos, Herramientas y Aplicaciones

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    Participation in a competitive project

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