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Concertina: Squeezing in cache content to operate at near-threshold voltage

Autor
Ferrerón, A.; Suárez, D.; Alastruey, J.; Monreal, T.; Ibáñez, P.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on computers
Data de publicació
2016-03-01
Volum
65
Número
3
Pàgina inicial
755
Pàgina final
769
DOI
https://doi.org/10.1109/TC.2015.2479585 Obrir en finestra nova
Projecte finançador
Computación de Altas Prestaciones VI
Repositori
http://hdl.handle.net/2117/88590 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7272076 Obrir en finestra nova
Resum
Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high density requirements. In this paper, we propose Concertina, an LLC designed to enable reliable oper...
Citació
Ferrerón, A., Suárez, D., Alastruey, J., Monreal, T., Ibáñez, P. Concertina: Squeezing in cache content to operate at near-threshold voltage. "IEEE transactions on computers", 01 Març 2016, vol. 65, núm. 3, p. 755-769.
Paraules clau
Fault-tolerance, Near-threshold voltage, On-chip caches, SRAM variability
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Ferrerón, Alexandra  (autor)
  • Suárez Gracía, Dario  (autor)
  • Alastruey, Jesús  (autor)
  • Monreal Arnal, Teresa  (autor)
  • Ibáñez, Pablo  (autor)

Arxius