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Adaptive runtime-assisted block prefetching on chip-multiprocessors

Autor
Garcia, V.; Rico, A.; Villavieja, C.; Carpenter, P.; Navarro, N.; Ramirez, A.
Tipus d'activitat
Article en revista
Revista
International journal of parallel programming
Data de publicació
2016-04-29
Pàgina inicial
1
Pàgina final
21
DOI
https://doi.org/10.1007/s10766-016-0431-8 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/100924 Obrir en finestra nova
URL
http://link.springer.com/article/10.1007%2Fs10766-016-0431-8 Obrir en finestra nova
Resum
Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled prefetching we find a wide variety of schemes, including runtime-directed prefetching and more specifically runtime-directed block prefetching. This paper proposes a hybrid prefetching mechanism that ...
Citació
Garcia, V., Rico, A., Villavieja, C., Carpenter, P., Navarro, N., Ramirez, A. Adaptive runtime-assisted block prefetching on chip-multiprocessors. "International journal of parallel programming", 29 Abril 2016, p. 1-21.
Paraules clau
Cache memories, Prefetch, Task based programming models
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Garcia Flores, Victor  (autor)
  • Rico Carro, Alejandro  (autor)
  • Villavieja Prados, Carlos  (autor)
  • Carpenter, Paul Matthew  (autor)
  • Navarro Mas, Nacho  (autor)
  • Ramirez, Alex  (autor)

Arxius