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A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects

Autor
Jain, P.; Cortadella, J.; Sapatnekar, S.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on very large scale integration (VLSI) systems
Data de publicació
2016-06-01
Volum
24
Número
6
Pàgina inicial
2345
Pàgina final
2358
DOI
https://doi.org/10.1109/TVLSI.2015.2505504 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/90714 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/7374743/?arnumber=7374743 Obrir en finestra nova
Resum
A new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and voltage-dependent pin capacitance in the library model. It additionally provides an on-the-fly retargeting capability for reliability constraints by allowing arbitrary specifications of lifetimes, temperatures, voltages, and failure rates, as well as interoperability of the IPs acro...
Citació
Jain, P., Cortadella, J., Sapatnekar, S. A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects. "IEEE transactions on very large scale integration (VLSI) systems", 1 Juny 2016, vol. 24, núm. 6, p. 2345-2358.
Paraules clau
Electromigration (em), Pin Capacitance, Reliability, Retargeting, Signal Probability, Timing Analysis, Interconnect, Models
Grup de recerca
ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals

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