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Shared resource aware scheduling on power-constrained tiled many-core processors

Autor
Jha, S.; Heirman, W.; Falcón, A.; Tubella, J.; Gonzalez, A.; Eeckhout, Lieven
Tipus d'activitat
Article en revista
Revista
Journal of parallel and distributed computing
Data de publicació
2017-02-01
Volum
100
Pàgina inicial
30
Pàgina final
41
DOI
https://doi.org/10.1016/j.jpdc.2016.10.001 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/97578 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/S0743731516301186 Obrir en finestra nova
Resum
Power management through dynamic core, cache and frequency adaptation is becoming a necessity in today’s power-constrained many-core environments. Unfortunately, as core count grows, the complexity of both the adaptation hardware and the power management algorithms increases exponentially. This calls for hierarchical solutions, such as on-chip voltage regulators per-tile rather than per-core, along with multi-level power management. As power-driven adaptation of shared resources affects multip...
Citació
Jha, S., Heirman, W., Falcon, A., Tubella, J., González, A., Eeckhout, Lieven. Shared resource aware scheduling on power-constrained tiled many-core processors. "Journal of parallel and distributed computing", 1 Febrer 2017, vol. 100, p. 30-41.
Paraules clau
Adaptive microarchitecture, Many-core tiled architecture, Power budget, Thread migration
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants