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Fitting processor architectures for measurement-based probabilistic timing analysis

Autor
Kosmidis, L.; Quiñones, E.; Abella, J.; Vardanega, T.; Hernandez, C.; Gianarro, A.; Broster, I.; Cazorla, F. J.
Tipus d'activitat
Article en revista
Revista
Microprocessors and microsystems
Data de publicació
2016-11-01
Volum
47
Número
Part B
Pàgina inicial
287
Pàgina final
302
DOI
https://doi.org/10.1016/j.micpro.2016.07.014 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/100471 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/S0141933116300977 Obrir en finestra nova
Resum
The pressing market demand for competitive performance/cost ratios compels Critical Real-Time Embedded Systems industry to employ feature-rich hardware. The ensuing rise in hardware complexity however makes worst-case execution time (WCET) analysis of software programs - which is often required, especially for programs at the highest levels of integrity - an even harder challenge. State-of-the-art WCET analysis techniques are hampered by the soaring cost and complexity of obtaining accurate know...
Citació
Kosmidis, L., Quiñones, E., Abella, J., Vardanega, T., Hernández, C., Gianarro, A., Broster, I., Cazorla, F. Fitting processor architectures for measurement-based probabilistic timing analysis. "Microprocessors and microsystems", 1 Novembre 2016, vol. 47, núm. Part B, p. 287-302.
Paraules clau
Cache memories, Probabilistic analysis, Processor architecture, Time randomization, Worst-case execution time
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Kosmidis, Leonidas  (autor)
  • Quiñones Moreno, Eduardo  (autor)
  • Abella Ferrer, Jaume  (autor)
  • Vardanega, Tullio  (autor)
  • Hernandez, Carles  (autor)
  • Gianarro, Andrea  (autor)
  • Broster, Ian  (autor)
  • Cazorla Almeida, Francisco Javier  (autor)