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Multiple-banked register file architectures

Autor
Cruz, J.; Gonzalez, A.; Valero, M.; Topham, N.
Tipus d'activitat
Article en revista
Revista
Computer architecture news
Data de publicació
2000-05
Volum
28
Número
2
Pàgina inicial
316
Pàgina final
325
DOI
https://doi.org/10.1145/342001.339708 Obrir en finestra nova
URL
http://dl.acm.org/citation.cfm?id=339708&CFID=736148909&CFTOKEN=22826653 Obrir en finestra nova
Resum
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor generations, as they are expected to increase the issue width (which implies more register ports) and the size of the instruction window (which implies more registers), and to use some kind of multithreading. Under this scenario, the register file access time could be a dominant delay and a pipelined implementation would be d...
Paraules clau
Bypass logic, Dynamically-scheduled processor, Register file architecture, Register file cache
Grup de recerca
ARCO - Microarquitectura i Compiladors
CAP - Grup de Computació d'Altes Prestacions

Participants