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DSPONE48 : a methodology for automatically synthesize HDL focus on the reuse of DSP slices

Autor
De Lucas, E.; Sanchez-Elez, M.; Pardines, I.
Tipus d'activitat
Article en revista
Revista
Journal of parallel and distributed computing
Data de publicació
2017-08-01
Volum
106
Pàgina inicial
132
Pàgina final
142
DOI
https://doi.org/10.1016/j.jpdc.2017.01.021 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/S0743731517300400 Obrir en finestra nova
Resum
This work proposes a methodology to synthesize arithmetic operations maximizing the reuse of the DSP48E1 blocks presented in the new reconfigurable architectures. The input for DSPONE48 is a VHDL code without any reference to the FPGA hardware resources. This input code is modified, so the synthesis tool is able to implement it with DSP slices. In order to achieve this objective we use DSP block instantiation templates and we encourage the use of SIMD mode within the DSP block. This methodology ...
Paraules clau
DSP, FPGA, System-level Design tools, VHDL
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants

  • De Lucas Casamayor, Enrique  (autor)
  • Sanchez Elez, Marcos  (autor)
  • Pardines, Inmaculada  (autor)