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1 to 11 of 11 results
  • M-S test based on specification validation using octrees in the measure space

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    IEEE European Test Symposium
    p. 70-75
    DOI: 10.1109/ETS.2013.6569359
    Presentation's date: 2013-05-28
    Presentation of work at congresses

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    Testing M-S circuits is a difficult task demanding high amount of resources. To overcome these drawbacks, indirect testing methods have been adopted as an efficient solution to perform specification based tests using easy to measure metrics. In this work, a testing technique using octrees in the measure space is presented. Octrees have been used in computer graphics with successful results for rendering, image processing and space clustering applications. In this paper are used to encode the test acceptance region with arbitrary precision after an statistical training phase. Such representation allows an efficient way to test a candidate circuit in terms of test application time. The method is applied to test a Biquad filter with encouraging results. Test escapes and test yield loss caused by parametric variations have been estimated.

  • Nondestructive diagnosis of mechanical misalignments in dual axis accelerometers

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Design, Test, Integration & Packaging of MEMS/MOEMS
    Presentation's date: 2013-04-18
    Presentation of work at congresses

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    Microelectromechanical systems production is still an immature technology compared to the classical semiconductor industry. MEMS fabrication and packaging processes may present misalignments which result in an improper placement of the internal microstructures or dies. In this work, the possibilities of diagnosing mechanical misalignments of dual axis IC accelerometers are explored. The used method dynamically correlates the two output signals in orthogonal directions. This leads to a Lissajous composition which is able to manifest the actual level of misalignment. The definition of a metric and its variation rate study allows the diagnosis procedure. Experimental results using a commercial dual axis capacitive accelerometer reveal diagnosis discrepancies as low as 1.1%, therefore showing the viability of the proposal.

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    Built-In test of MEMS capacitive accelerometers for field failures and aging degradation.  Open access

     Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Design of Circuits and Integrated Systems Conference
    p. 223-228
    Presentation's date: 2012-11-28
    Presentation of work at congresses

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    SRAM stability metric under transient noise  Open access

     Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pamies, Juan
    Design of Circuits and Integrated Systems Conference
    Presentation's date: 2012-11-30
    Presentation of work at congresses

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    ventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mi smatch variations, bulk noises, supply rings variations, temperature changes is well characterized by means of the Static Noise Margin (SNM) defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. However, a significant number of disturbance sources present a transient behavior which is ignored by the static analysis but has to be taken in consideration for a complete characterization of the cell’s behavior. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage noise is proposed based on determining the energy of the noise signal which is able to flip the cell’s state. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage noise signal able to flip the cell.

  • Testing IC accelerometers using Lissajous compositions

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Perspective Technologies and Methods in MEMS Design
    p. 75-81
    Presentation's date: 2011-05-11
    Presentation of work at congresses

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    Micro Electro Mechanical devices (MEMs) have widened their range of applications in a spectacular way in the last years. Reliability of MEMs devices is one of the areas that need to be improved to achieve high volume production at allowable costs. Accelerometers have in their design some mechanical and layout symmetries that can be used to improve the test and diagnosis results. In our approach we take profit of the symmetries of dual axis accelerometers to analyze and test its behavior using a procedure that composes the two orthogonal outputs when the accelerometer is spun. The complexity in the kinematics seen by the sensitive axes of the accelerometer yields rich and complex Lissajous traces that characterize the device and allows to determine the possible mismatchings in the assumed damped mass model parameters. In order to compare and quantify parameter discrepancies, a metric has been defined to allow to determine whether the DUT is within specifications or not.

  • Transient noise failures in SRAM cells : dynamic noise margin metric

     Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pamies, Juan
    Asian Test Symposium
    p. 413-418
    DOI: 10.1109/ATS.2011.64
    Presentation's date: 2011
    Presentation of work at congresses

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    Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and environmental aggressions such as RF or on-chip couplings. In the case of SRAM cells, the static immunity to such perturbations is well characterized by means of the Static Noise Margin (SNM)defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. In addition, a significant number of disturbance sources present a transient behavior which has to be taken in consideration. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage signals is proposed. Sufficiently high energy noise signals will compel the cell to flip to a failure state. On the other hand, sufficiently low energy noise signals will not be able to flip the cell and the state will be preserved. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage pulses able to flip the cell. A case example of transient voltage noise pulses on a 6T SRAM cell using 45nm technology has been studied. Simulation results show the use of the proposed metric as an indicator of cell robustness in the presence of transient voltage noise

  • Testing dual axis IC accelerometers using Lissajous compositions

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    p. 1-4
    Presentation's date: 2011-11-17
    Presentation of work at congresses

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  • Identification of component deviations in analog circuits using digital signatures

     Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    p. 187-192
    Presentation's date: 2010-11-17
    Presentation of work at congresses

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    Analog circuit test based on a digital signature  Open access

     Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Design, Automation and Test in Europe
    p. 1641-1644
    Presentation's date: 2010-03-08
    Presentation of work at congresses

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    Production verification of analog circuit specifica- tions is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost on-chip parameter verification based on the analysis of a digital signature. A 65 nm CMOS on-chip monitor is proposed and validated in practice. The monitor composes two signals (x(t), y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x, y) location. A digital signature is obtained using the digital code and its time duration. A metric defining a discrepancy factor is used to verify circuit parameters. The method is applied to detect possible deviations in the natural frequency of a Biquad filter. Simulated and experimental results show the possibilities of the proposal.

    Production verification of analog circuit specifica- tions is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost on-chip parameter verification based on the analysis of a digital signature. A 65 nm CMOS on-chip monitor is proposed and validated in practice. The monitor composes two signals (x(t), y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x, y) location. A digital signature is obtained using the digital code and its time duration. A metric defining a discrepancy factor is used to verify circuit parameters. The method is applied to detect possible deviations in the natural frequency of a Biquad filter. Simulated and experimental results show the possibilities of the proposal.

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    Verifying analog circuits based on a digital signature  Open access

     Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    p. 1-6
    Presentation's date: 2009-11-18
    Presentation of work at congresses

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    Veri¿cation of analog circuit speci¿cations is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost parameter veri¿cation based on statistical analysis of a digital signature. A CMOS on-chip monitor and sampler circuit generates the digital signature of the CUT. The monitor composes two signals (x(t), y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x, y) location. A metric to be used to discriminate the golden and defective signatures is also proposed. The metric is based on the de¿nition of a discrepancy factor performing circuit parameter identi¿cation via statistical and pre-training procedures. The proposed method is applied to verify possible deviations on the natural frequency of a Biquad ¿lter. Simulation results show the possibilities of the proposal.

    Verification of analog circuit specifications is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost parameter verification based on statistical analysis of a digital signature. A CMOS on-chip monitor and sampler circuit generates the digital signature of the CUT. The monitor composes two signals (x(t); y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x; y) location. A metric to be used to discriminate the golden and defective signatures is also proposed. The metric is based on the definition of a discrepancy factor performing circuit parameter identification via statistical and pre-training procedures. The proposed method is applied to verify possible deviations on the natural frequency of a Biquad filter. Simulation results show the possibilities of the proposal.

  • Digital signature generator for mixed-signal testing

     Sanahuja Moliner, Ricard; Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    IEEE European Test Symposium
    Presentation's date: 2009-05-26
    Presentation of work at congresses

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