Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan; Chatterjee, Abhijit Conference on Design of Circuits and Integrated Systems p. 1-6 Presentation's date: 2014-11-28 Presentation of work at congresses
Gómez Pau, Álvaro; Banerjee, Suvadeep; Chatterjee, Abhijit IEEE International On-Line Testing Symposium p. 25-30 DOI: 10.1109/IOLTS.2014.6873667 Presentation's date: 2014-07 Presentation of work at congresses
Analog circuits are sensitive to signal aggressions and power supply noise, crosstalk coupling and alpha particle strikes can cause significant degradation of circuit's SNR. This research proposes a novel approach to real-time transient error and induced noise cancellation in linear analog circuits using analog checksums. It is based on the use of state space representations of analog filters and is a significant advancement over prior research that addressed only hard parametric deviations. A key innovation is the use of less than minimum distance checksum codes for error detection and correction using real-time learning of the likely source of transient errors and noise within the analog circuit. By running a simple hardware-directed search algorithm, the circuit 'learns' how best to compensate for the injected signal disturbances with low overhead under the assumption that the source of the injected errors/noise and the error/noise statistics are stationary over time. Successful simulations and preliminary experimental results demonstrate almost complete compensation of injected noise, therefore validating the proposal.
Analog and mixed-signal circuit testing is a cballenging
task demanding large amounts of resources. In order to battle
against this drawback, alternate testing has been established as an
eflicient way of testing analog and M-S circuits by using indirect
measures instead of the classic specification based testing. In
this work we propose the use of Kendall's Tau rank correlation
coeflicient for rating the suitability of a set of candidate indirect
measures to be used in mixed-signal testing. Such criterion is
shown to be adequate since it allows to avoid or minimize
information redundancy in the measures set. As a proof of
concept, a 4th order band-pass Butterworth filter has been
simulated under the presence of process variations. The circuit
has been tested using a subset of measures selected according to
minimum Kendall's Tau coeflicient. Analog test efliciency metrics
are reported showing test misclassification rate is among the best
15% possible, therefore validating the proposal.
Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan IEEE European Test Symposium p. 70-75 DOI: 10.1109/ETS.2013.6569359 Presentation's date: 2013-05-28 Presentation of work at congresses
Testing M-S circuits is a difficult task demanding high amount of resources. To overcome these drawbacks, indirect
testing methods have been adopted as an efficient solution to perform specification based tests using easy to measure metrics.
In this work, a testing technique using octrees in the measure space is presented. Octrees have been used in computer graphics
with successful results for rendering, image processing and space clustering applications. In this paper are used to encode the test acceptance region with arbitrary precision after an statistical
training phase. Such representation allows an efficient way to test a candidate circuit in terms of test application time. The method
is applied to test a Biquad filter with encouraging results. Test escapes and test yield loss caused by parametric variations have been estimated.
Microelectromechanical systems production is still an immature technology compared to the classical semiconductor industry. MEMS fabrication and packaging processes may
present misalignments which result in an improper placement of the internal microstructures or dies. In this work, the
possibilities of diagnosing mechanical misalignments of dual axis IC accelerometers are explored. The used method dynamically
correlates the two output signals in orthogonal directions. This leads to a Lissajous composition which is able to manifest the actual level of misalignment. The definition of a metric and its variation rate study allows the diagnosis procedure.
Experimental results using a commercial dual axis capacitive accelerometer reveal diagnosis discrepancies as low as 1.1%, therefore showing the viability of the proposal.
ventional way to analyze the robustness of an
SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mi smatch variations, bulk noises, supply rings variations, temperature changes is well characterized by means of the Static Noise
Margin (SNM) defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes.
However, a significant number of disturbance sources present a transient behavior which is ignored by the static analysis but has
to be taken in consideration for a complete characterization of the cell’s behavior. In this paper, a metric to evaluate the cell
robustness in the presence of transient voltage noise is proposed based on determining the energy of the noise signal
which is able to flip the cell’s state. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage noise signal able to flip the cell.
Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan Conference on Design of Circuits and Integrated Systems p. 223-228 Presentation's date: 2012-11-28 Presentation of work at congresses
Micro Electro Mechanical devices (MEMs) have
widened their range of applications in a spectacular way in
the last years. Reliability of MEMs devices is one of the areas
that need to be improved to achieve high volume production
at allowable costs. Accelerometers have in their design some
mechanical and layout symmetries that can be used to improve
the test and diagnosis results. In our approach we take profit of
the symmetries of dual axis accelerometers to analyze and test
its behavior using a procedure that composes the two orthogonal
outputs when the accelerometer is spun. The complexity in
the kinematics seen by the sensitive axes of the accelerometer
yields rich and complex Lissajous traces that characterize the
device and allows to determine the possible mismatchings in the
assumed damped mass model parameters. In order to compare
and quantify parameter discrepancies, a metric has been defined
to allow to determine whether the DUT is within specifications
Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and environmental aggressions such as RF or on-chip couplings. In the case of SRAM cells, the static immunity to such perturbations is well characterized by means of the Static Noise Margin (SNM)defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. In addition, a significant number of disturbance sources present a transient behavior which has to be taken in consideration. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage signals is proposed. Sufficiently high energy noise signals will compel the cell to flip to a failure state. On the other hand, sufficiently low energy noise signals will not be able to flip the cell and the state will be preserved. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage pulses able to flip the cell. A case example of transient voltage noise pulses on a 6T SRAM cell using 45nm technology has been studied. Simulation results show the use of the proposed metric as an indicator of cell robustness in the presence of transient voltage noise
Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan Conference on Design of Circuits and Integrated Systems p. 187-192 Presentation's date: 2010-11-17 Presentation of work at congresses
Analog circuits component diagnosis is a challenging
task requiring expensive resources. This paper presents a low
cost method to identify deviations in multiple component values
using a precharacterisation of the impact of the deviations on
the digital signatures for a set of input excitations. The method
predicts several circuit under diagnosis (CUD) deviations by
mapping them to a scalar value that indicates the discrepancy
of the defective and golden digital signatures. Input excitation
consists of a small set of sinusoidal signals with different
frequencies. A digital signature is generated for every excitation
set and compared to the golden response. The scalar discrepancy
values are used to obtain the component deviations of the CUD.
In order to generate the signatures, a CMOS monitor circuit
has been designed and fabricated. The method is applied to
the identification of capacitance deviations in a Biquad filter.
Simulated results show the possibilities of the proposal
Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan Design, Automation and Test in Europe p. 1641-1644 Presentation's date: 2010-03-08 Presentation of work at congresses
Production verification of analog circuit specifica-
tions is a challenging task requiring expensive test equipment
and time consuming procedures. This paper presents a method
for low cost on-chip parameter verification based on the analysis
of a digital signature. A 65 nm CMOS on-chip monitor is
proposed and validated in practice. The monitor composes two
signals (x(t), y(t)) and divides the X-Y plane with nonlinear
boundaries in order to generate a digital code for every analog
(x, y) location. A digital signature is obtained using the digital
code and its time duration. A metric defining a discrepancy factor
is used to verify circuit parameters. The method is applied to
detect possible deviations in the natural frequency of a Biquad
filter. Simulated and experimental results show the possibilities
of the proposal.