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A first glance at the stream decoding architecture

Autor
Santana, O.; Falcón, A.; Ramírez , A.; Valero, M.
Tipus d'activitat
Document cientificotècnic
Data
2004-06
Codi
UPC-DAC-2004-26
Resum
Fast instruction decoding is a challenge for the design of processors implementing variable length instruction set architectures. The trace cache is a widely used technique for implementing an efficient decoding mechanism. It stores and fetches already decoded instructions, avoiding the need for decoding them again. However, implementing a trace cache involves an important increase in the fetch architecture complexity. In this paper, we propose a novel decoding architecture which avoids such an ...
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Santana Jaria, Oliverio J.  (autor)
  • Falcón Samper, Ayose Jesús  (autor)
  • Ramírez Bellido, Alejandro  (autor)
  • Valero Cortes, Mateo  (autor)