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Future ILP processors

Autor
Cristal, A.; Llosa, J.; Valero, M.; Ortega, D.
Tipus d'activitat
Article en revista
Revista
International journal of high performance computing and networking
Data de publicació
2004
Volum
2
Número
1
Pàgina inicial
1
Pàgina final
10
DOI
https://doi.org/10.1504/IJHPCN.2004.009263 Obrir en finestra nova
URL
http://www.inderscience.com/dev/search/index.php?mainAction=search&action=record&rec_id=9263&prevQuery=&ps=10&m=or Obrir en finestra nova
Resum
Memory speed is growing more slowly than processor speed. This means that processors must spend more and more time waiting for data to arrive from memory. One of the most effective techniques to deal with this effect is to increase the amount of in-flight instructions in the processor, thus allowing for an increased instruction level parallelism when missing instructions occur. With expected latencies of 500 and 1000 cycles, the amount of in-flight instructions needed to sustain performance will...
Paraules clau
High performance computing, ILP processors, In-flight instructions, Instruction level parallelism, Instruction queues, Memory latencies, Microarchitecture, Out-of-order processors, Registers, Reorder buffers, Superscalar design
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants