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Dynamic memory instruction bypassing

Autor
Ortega, D.; Valero, M.; Ayguade, E.
Tipus d'activitat
Article en revista
Revista
International journal of parallel programming
Data de publicació
2004-06
Volum
32
Número
3
Pàgina inicial
199
Pàgina final
224
DOI
https://doi.org/10.1023/B:IJPP.0000029273.49634.19 Obrir en finestra nova
URL
https://link.springer.com/article/10.1023/B%3AIJPP.0000029273.49634.19 Obrir en finestra nova
Resum
Reducing the latency of load instructions is among the most crucial aspects to achieve high performance for current and future microarchitectures. Deep pipelining impacts load-to-use latency even for loads that hit in cache. In this paper we present a dynamic mechanism which detects relations between address producing instructions and the loads that consume these addresses and uses this information to access data before the load is even fetched from the I-Cache. This mechanism is not intended to...
Paraules clau
Memory bypassing, Prefetching
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants