Carregant...
Carregant...

Vés al contingut (premeu Retorn)

An optimized front-end physical register file with banking and writeback filtering

Autor
Pericàs, M.; González, R.; Veidenbaum, A.; Cristal, A.; Valero, M.
Tipus d'activitat
Article en revista
Revista
Lecture notes in computer science
Data de publicació
2005
Volum
3471
Pàgina inicial
1
Pàgina final
14
DOI
https://doi.org/10.1007/11574859_1 Obrir en finestra nova
URL
https://link.springer.com/chapter/10.1007/11574859_1 Obrir en finestra nova
Resum
Register file design is one of the critical issues facing designers of out–of–order processors. Scaling up its size and number of ports with issue width and instruction window size is difficult in terms of both performance and power consumption. Two types of register file architectures have been proposed in the past: a future logical file and a centralized physical file. The centralized register file does not scale well but allows fast branch mis–prediction recovery. The Future File scales...
Paraules clau
Computer power supplies, Logic design, Memory architecture, Microprocessor chips
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants