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Exploiting execution locality with a decoupled kilo-instruction processor

Autor
Pericàs, M.; Cristal, A.; González, R.; Jiménez, D. A.; Valero, M.
Tipus d'activitat
Article en revista
Revista
Lecture notes in computer science
Data de publicació
2008
Volum
4759
Pàgina inicial
56
Pàgina final
67
DOI
https://doi.org/10.1007/978-3-540-77704-5_5 Obrir en finestra nova
URL
https://link.springer.com/chapter/10.1007/978-3-540-77704-5_5 Obrir en finestra nova
Resum
Overcoming increasing memory latency is one of the main problems that microprocessor designers have faced over the years. The two basic techniques introduced to mitigate latencies are caches and out-of-order execution. However, neither of these solutions is adequatefor hiding off-chip memory accesses in the order of 200 cycles or more. Theoretically, increasing the size of the instruction window would allow much longer latencies to be hidden. But scaling the structures to support thousands of in...
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Pericàs, Miquel  (autor)
  • Cristal Kestelman, Adrián  (autor)
  • González, Rubén  (autor)
  • Jiménez, Daniel A.  (autor)
  • Valero Cortes, Mateo  (autor)