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An integrated vector-scalar design on an in-order ARM core

Autor
Stanic, M.; Palomar, Ó.; Hayes, T.; Ratkovic, I.; Cristal, A.; Unsal, O.; Valero, M.
Tipus d'activitat
Article en revista
Revista
ACM transactions on architecture and code optimization
Data de publicació
2017-07
Volum
14
Número
2
Pàgina inicial
1
Pàgina final
26
DOI
https://doi.org/10.1145/3075618 Obrir en finestra nova
Projecte finançador
Computación de Altas Prestaciones VII
Repositori
http://hdl.handle.net/2117/106671 Obrir en finestra nova
URL
http://dl.acm.org/citation.cfm?id=3075618 Obrir en finestra nova
Resum
In the low-end mobile processor market, power, energy, and area budgets are significantly lower than in the server/desktop/laptop/high-end mobile markets. It has been shown that vector processors are a highly energy-efficient way to increase performance; however, adding support for them incurs area and power overheads that would not be acceptable for low-end mobile processors. In this work, we propose an integrated vector-scalar design for the ARM architecture that mostly reuses scalar hardware ...
Citació
Stanic, M., Palomar, Ó., Hayes, T., Ratkovic, I., Cristal, A., Unsal, O., Valero, M. An integrated vector-scalar design on an in-order ARM core. "ACM transactions on architecture and code optimization", Juliol 2017, vol. 14, núm. 2, p. 17:1-17:26.
Paraules clau
Computer systems organization, Energy efficiency, Low-power, Mobile processors, Multiple data, Single instruction, Vector processors
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Stanic, Milan  (autor)
  • Palomar Pérez, Óscar  (autor)
  • Hayes, Timothy  (autor)
  • Ratkovic, Ivan  (autor)
  • Cristal Kestelman, Adrián  (autor)
  • Unsal, Osman Sabri  (autor)
  • Valero Cortes, Mateo  (autor)