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Thread lock section-aware scheduling on asymmetric single-ISA multi-core

Autor
Markovic, N.; Nemirovsky, D.; Unsal, O.; Valero, M.; Cristal, A.
Tipus d'activitat
Article en revista
Revista
IEEE computer architecture letters
Data de publicació
2015-07
Volum
14
Número
2
Pàgina inicial
160
Pàgina final
163
DOI
https://doi.org/10.1109/LCA.2014.2357805 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/6899614/ Obrir en finestra nova
Resum
As thread level parallelism in applications has continued to expand, so has research in chip multi-core processors. As more and more applications become multi-threaded we expect to find a growing number of threads executing on a machine. As a consequence, the operating system will require increasingly larger amounts of CPU time to schedule these threads efficiently. Instead of perpetuating the trend of performing more complex thread scheduling in the operating system, we propose a scheduling mec...
Paraules clau
Microprocessor chips, Multi-threading, Multiprocessing systems, Operating systems (computers), Scheduling
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Markovic, Nikola  (autor)
  • Nemirovsky, Daniel  (autor)
  • Unsal, Osman Sabri  (autor)
  • Valero Cortes, Mateo  (autor)
  • Cristal Kestelman, Adrián  (autor)