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Reimagining heterogeneous computing: A functional instruction-set architecture computing model

Autor
Nemirovsky, D.; Markovic, N.; Unsal, O.; Valero, M.; Cristal, A.
Tipus d'activitat
Article en revista
Revista
IEEE micro
Data de publicació
2015-09
Volum
35
Número
5
Pàgina inicial
6
Pàgina final
14
DOI
https://doi.org/10.1109/MM.2015.109 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/7310930/ Obrir en finestra nova
Resum
The relentless push in technology scaling driven by Moore's law has witnessed fantastic gains in the quantities of transistors available on chips. Computer architects have exploited the extra transistors by incorporating several computing cores within a single processor. Heterogeneous processing in particular has become a useful technique for dealing with ever-present power and memory restrictions. Yet, the scope and diversity of current heterogeneous designs remain bounded by the level of funct...
Paraules clau
F-ISA, Heterogeneous (hybrid) systems, High-level language architectures, Instruction set design, Micro, Multi-core/single-chip multiprocessors, Processor architectures
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Nemirovsky, Daniel  (autor)
  • Markovic, Nikola  (autor)
  • Unsal, Osman Sabri  (autor)
  • Valero Cortes, Mateo  (autor)
  • Cristal Kestelman, Adrián  (autor)