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A novel architecture for large windows processors

Autor
González, I.; Galluzzi, M.; Veidenbaum, A.; Ramirez, M.; Cristal, A.; Valero, M.
Tipus d'activitat
Document cientificotècnic
Data
2007-11
Codi
UPC-DAC-RR-CAP-2007-34
Repositori
http://hdl.handle.net/2117/108137 Obrir en finestra nova
Resum
Several processor architectures with large instruction windows have been proposed. They improve performance by maintaining hundreds of instructions in flight to increase the level of instruction parallelism (ILP). Such architectures replace a re-order buffer (ROB) with a check-pointing mechanism and an out-of-order release of the processor resources. Check-pointing, however, leads to an imprecise state recovery on mispredicted branches and exceptions and frequent re-execution of current-path ins...
Citació
González, I., Galluzzi, M., Veidenbaum, A., Ramírez, M., Cristal, A., Valero, M. "A novel architecture for large windows processors". 2007.
Paraules clau
Recovery, Checkpoint, Renaming
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • González, Isidro  (autor)
  • Galluzzi, Marco  (autor)
  • Veidenbaum, Alex  (autor)
  • Ramírez, Marco Antonio  (autor)
  • Cristal Kestelman, Adrián  (autor)
  • Valero Cortes, Mateo  (autor)

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