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Characterizing the resource-sharing levels in the UltraSPARC T2 processor

Autor
Radojkovic, P.; Cakarevic, V.; Verdu, J.; Pajuelo, M.A.; Cazorla, F. J.; Nemirovsky, M.; Valero, M.
Tipus d'activitat
Document cientificotècnic
Data
2009
Codi
UPC-DAC-RR-CAP-2009-27
Resum
Thread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading (SMT) or Chip-Multiprocessors (CMP), provides different benefits, which has motivated processor vendors to combine several TLP paradigms in each chip design. Even if most of these combined-TLP designs are homogeneous, they present different levels of hardware resource sharing, which introduc...
Paraules clau
Multicore, Multithreaded, Resource Sharing, Performance Validation, Real Systems
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions
VIRTUOS - Virtualisation and Operating Systems

Participants