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Castell: A CMP architecture scalable to hundreds of processors

Autor
Cabarcas, F.; Rico, A.; Ramírez , A.; Etsion, Y.; Villavieja, C.; Vega, A.; Pavlovic, M.; Quesada, A.; Bellens, P.; Badia, R.M.; Valero, M.
Tipus d'activitat
Document cientificotècnic
Data
2009
Codi
UPC-DAC-RR-CAP-2009-33
Resum
The current interpretation of Moore's Law is that the number of cores per chip will double every 18 months, leading to architectures with more than 100 cores by 2015. However, it is not clear if current SMP architectures will scale that far, or how such multicores will be programmed. In this paper we present the Castell CMP architecture and its task-based programming model. The master-worker programming model naturally leads to an heterogeneous architecture. We show how we deal with high memory...
Paraules clau
Cmp, Scalable Architecture
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Cabarcas Jaramillo, Felipe  (autor)
  • Rico, Alejandro  (autor)
  • Ramírez Bellido, Alejandro  (autor)
  • Etsion, Yoav  (autor)
  • Villavieja, Carlos  (autor)
  • Vega, Augusto  (autor)
  • Pavlovic, Milan  (autor)
  • Quesada, Antonio  (autor)
  • Bellens, Pieter  (autor)
  • Badia Sala, Rosa Maria  (autor)
  • Valero Cortes, Mateo  (autor)