Carregant...
Carregant...

Vés al contingut (premeu Retorn)

OrthoNoC: a broadcast-oriented dual-plane wireless network-on-chip architecture

Autor
Abadal, S.; Torrellas Jovani, Josep; Alarcon, E.; Albert Cabellos-Aparicio
Tipus d'activitat
Article en revista
Revista
IEEE transactions on parallel and distributed systems
Data de publicació
2017-10-20
DOI
https://doi.org/10.1109/TPDS.2017.2764901 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/111962 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/8078211/ Obrir en finestra nova
Resum
On-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and architectural flexibility. Particularly, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. This work presents ORTHONOC, a wired-wireless architecture that differs f...
Citació
Abadal, S., Torrellas Jovani, Josep, Alarcon, E., A. C. OrthoNoC: a broadcast-oriented dual-plane wireless network-on-chip architecture. "IEEE transactions on parallel and distributed systems", 20 Octubre 2017.
Paraules clau
Bandwidth, Broadcast, Coherence, Hybrid NoC, Manycore Processors, Network-on-Chip, Program processors, Scalability, System-on-chip, Throughput, Wireless On-Chip Communication, Wireless communication
Grup de recerca
CBA - Sistemes de Comunicacions i Arquitectures de Banda Ampla
EPIC - Energy Processing and Integrated Circuits
PERC-UPC - Centre de Recerca d'Electrònica de Potència UPC

Participants

Arxius