Carregant...
Carregant...

Vés al contingut (premeu Retorn)

Systolic implementation for deconvolution iterative algorithm

Autor
Navarro, J.; Casares, V.
Tipus d'activitat
Document cientificotècnic
Data
1985
Codi
RR 85/19
Repositori
http://hdl.handle.net/2117/110915 Obrir en finestra nova
Resum
Systolic architectures implement regular algorithms in hardware, in order to obtain high computational throughput. In this paper we provide a modular architecture for a deconvolution iterative algorithm. The basic module is a systolic array which implement one iteration of the algorithm recentley proposed in 1. The algorithm is a generalization of the method to invert non singular polynomial transfer function, previously publoshed in 2. The basic systoloc module can be repeteadly concatenated i...
Citació
Navarro, J., Casares, V. "Systolic implementation for deconvolution iterative algorithm". 1985.
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

Arxius