Carregant...
Carregant...

Vés al contingut (premeu Retorn)

Reducing cache coherence traffic with a NUMA-aware runtime approach

Autor
Caheny, P.; Alvarez, L.; Derradji, S.; Valero, M.; Moreto, M.; Casas, M.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on parallel and distributed systems
Data de publicació
2018-05
Volum
29
Número
5
Pàgina inicial
1174
Pàgina final
1187
DOI
https://doi.org/10.1109/TPDS.2017.2787123 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/116365 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/8239832/ Obrir en finestra nova
Resum
Cache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves programmability. However, ccNUMA architectures require sophisticated and expensive cache coherence protocols to enforce correctness during parallel executions, which trigger a significant amount of on- and off-chip traffic in the system. This paper analyses how coherence traffic may b...
Citació
Caheny, P., Alvarez, L., Derradji, S., Valero, M., Moreto, M., Casas, M. Reducing cache coherence traffic with a NUMA-aware runtime approach. "IEEE transactions on parallel and distributed systems", Maig 2018, vol. 29, núm. 5, p. 1174-1187.
Paraules clau
Cache Coherence, Numa, Task-based Programming Models
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants