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Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Autor
Champac, V.; Avendaño, V.; Figueras, J.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on very large scale integration (VLSI) systems
Data de publicació
2010-02
Volum
18
Número
2
Pàgina inicial
256
Pàgina final
269
DOI
https://doi.org/10.1109/TVLSI.2008.2010398 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/7805 Obrir en finestra nova
URL
http://sciencestage.com/d/5625290/built-in-sensor-for-signal-integrity-faults-in-digital-interconnect-signals.html Obrir en finestra nova
Resum
Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors...
Citació
Champac, V.; Avendaño, V.; Figueras, J. Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals. "IEEE transactions on very large scale integration (VLSI) systems", Febrer 2010, vol. 18, núm. 2, p. 256-269.
Grup de recerca
CRnE - Centre de Recerca en Ciència i Enginyeria Multiescala de Barcelona
QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat

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