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Thread to core assignment in SMT on-chip multiprocessors

Autor
Acosta, C. A.; Cazorla, F. J.; Alex Ramirez; Valero, M.
Tipus d'activitat
Article en revista
Revista
Computer architecture news
Data de publicació
2009
Pàgina inicial
67
Pàgina final
74
DOI
https://doi.org/10.1109/SBAC-PAD.2009.13 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/6860 Obrir en finestra nova
URL
http://portal.acm.org/citation.cfm?id=1685045 Obrir en finestra nova
Resum
State-of-the-art high-performance processors like the IBM POWER5 and Intel i7 show a trend in industry towards on-chip Multiprocessors (CMP) involving Simultaneous Multithreading (SMT) in each core. In these processors, the way in which applications are assigned to cores plays a key role in the performance of each application and the overall system performance. In this paper we show that the system throughput highly depends on the Thread to Core Assignment (TCA), regardless the SMT Instruction F...
Citació
Acosta, C. A. [et al.]. Thread to core assignment in SMT on-chip multiprocessors. "International symposium on computer architecture. Proceedings", 2009, p. 67-74.
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Acosta Ojeda, Carmelo Alexis  (autor)
  • Cazorla Almeida, Francisco Javier  (autor)
  • Ramirez Bellido, Alejandro  (autor)
  • Valero Cortes, Mateo  (autor)

Arxius