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Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add

Autor
Ratkovic, I.; Palomar, Ó.; Stanic, M.; Unsal, O.; Cristal, A.; Valero, M.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on very large scale integration (VLSI) systems
Data de publicació
2018-04-04
Volum
26
Número
4
Pàgina inicial
639
Pàgina final
652
DOI
https://doi.org/10.1109/TVLSI.2017.2784807 Obrir en finestra nova
Projecte finançador
Computación de altas prestaciones VII
Repositori
http://hdl.handle.net/2117/116231 Obrir en finestra nova
URL
https://ieeexplore.ieee.org/document/8252727/ Obrir en finestra nova
Resum
The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market that they are entering now. Floating-point (FP) fused multiply-add (FMA), being a functional unit with high power consumption, deserves special attention. Although clock gating is a well-known method to reduce switching power in synchronous designs, there are unexplored opport...
Citació
Ratkovic, I., Palomar, Ó., Stanic, M., Unsal, O., Cristal, A., Valero, M. Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add. "IEEE transactions on very large scale integration (VLSI) systems", 4 Abril 2018, vol. 26, núm. 4, p. 639-652.
Paraules clau
Clock-gating, Digital Arithmetic, Fused Multiply-add, Low Power, Methodologies, Vector Processors
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Ratkovic, Ivan  (autor)
  • Palomar Pérez, Óscar  (autor)
  • Stanic, Milan  (autor)
  • Unsal, Osman Sabri  (autor)
  • Cristal Kestelman, Adrián  (autor)
  • Valero Cortes, Mateo  (autor)

Arxius