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Improving branch prediction and predicated execution in out-of-order processors

Autor
Quiñones, E.; Parcerisa, Joan-Manuel; Gonzalez, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
13th International Symposium on High-Performance Computer Architecture
Any de l'edició
2007
Data de presentació
2007
Llibre d'actes
2007 IEEE 13th International Symposium on High Performance Computer Architecture
Pàgina inicial
75
Pàgina final
84
Editor
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/HPCA.2007.346186 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/96823 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/4147649/ Obrir en finestra nova
Resum
If-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Although it is globally beneficial, it has a negative side-effect because the removal of branches eliminates useful correlation information necessary for conventional branch predictors. The remaining branches may become harder to predict. However, in predicated ISAs with a compare-branch model, the correlation information not...
Citació
Quiñones, E., Parcerisa, Joan-Manuel, González, A. Improving branch prediction and predicated execution in out-of-order processors. A: International Symposium on High-Performance Computer Architecture. "2007 IEEE 13th International Symposium on High Performance Computer Architecture". Phoenix, AZ: Institute of Electrical and Electronics Engineers (IEEE), 2007, p. 75-84.
Paraules clau
Out Of Order, Accuracy, Instruction Sets, Computer Aided Instruction, Degradation, Registers, Hardware, Pipelines, Proposals, Costs
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants

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