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Local scheduling techniques for memory coherence in a clustered VLIW processor with a distributed data cache

Autor
Gibert, E.; Sánchez, J.; Gonzalez, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
International Symposium on Code Generation and Optimization 2003
Any de l'edició
2003
Data de presentació
2003
Llibre d'actes
International Symposium on Code Generation and Optimization, CGO 2003: 23-26 March 2003, San Francisco, California
Pàgina inicial
193
Pàgina final
203
Editor
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/CGO.2003.1191545 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/100451 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/1191545/ Obrir en finestra nova
Resum
Clustering is a common technique to deal with wire delays. Fully-distributed architectures, where the register file, the functional units and the cache memory are partitioned, are particularly effective to deal with these constraints and besides they are very scalable. However the distribution of the data cache introduces a new problem: memory instructions may reach the cache in an order different to the sequential program order, thus possibly violating its contents. In this paper two local sche...
Citació
Gibert, E., Sánchez, J., González, A. Local scheduling techniques for memory coherence in a clustered VLIW processor with a distributed data cache. A: International Symposium on Code Generation and Optimization. "International Symposium on Code Generation and Optimization, CGO 2003: 23-26 March 2003, San Francisco, California". San Francisco, CA: Institute of Electrical and Electronics Engineers (IEEE), 2003, p. 193-203.
Paraules clau
Interleaved Storage, Processor Scheduling, Synchronisation, Parallel Architectures, Cache Storage, Parallel Memories
Grup de recerca
ARCO - Microarquitectura i Compiladors

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