Dominguez, M.; Gorreta, S.; Pons, J.; Gomez, F.; Gonzalez, D. Microelectronics reliability Vol. 55, num. 9-10, p. 1926-1931 DOI: 10.1016/j.microrel.2015.06.084 Data de publicació: 2015-07-03 Article en revista
The purpose of this paper is to show that the charge induced by radiation in a dielectric on which a sigma–delta control of dielectric charge is implemented, can be seen as a disturbance in a sliding mode controller. Preliminary experimental results are presented in which a MEMS device is irradiated with X-rays, while the dielectric charge control is continuously being monitored. The charge induced by radiation generates a change in the control bitstream, which is associated with the presence of an external disturbance on the governing control equations.
Carbon nanotube field-effect transistors (CNFETs) are promising candidates to substitute silicon transistors. Boasting extraordinary electronic properties, CNFETs exhibit characteristics rivaling those of state-of-the-art Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). However, as any technology that is in development, CNFET fabrication process still have some imperfections that results in carbon nanotube variations, which can have a severe impact on the devices' performance and jeopardize their reliability (in this work the term reliability means time-zero failure due to manufacturing variations). This paper presents a study of the effects on transistors of the main CNFET manufacturing imperfections, including the presence of metallic carbon nanotubes (m-CNTs), imperfect m-CNT removal processes, chirality drift, CNT doping variations in the source/drain extension regions, and density fluctuations due to non-uniform inter-CNT spacing.
Calomarde, A.; Amat, Esteve; Moll, F.; Vigara, J.; Rubio, A. Microelectronics reliability Vol. 54, num. 4, p. 738-745 DOI: 10.1016/j.microrel.2013.12.018 Data de publicació: 2014-04-01 Article en revista
In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable operation of integrated circuits. This paper presents a novel design style which reduces the impact of radiation-induced single event transients (SET) on logic circuits, and enhances the robustness in noisy environments. The independent design style of this method achieves SET mitigation and noise immunity by strengthening the sensitive nodes using a technique similar to feedback. A realization for this methodology is presented in 7 nm FinFET and in order to check the accuracy of our proposal, we compare it with others techniques for hardening radiation at the transistor level against a single event transient. Simulation results show that the proposed method has a good soft error tolerance capability as well as better noise immunity.
Berbel, N.; Fernandez-Garcia, R.; Gil, I.; Li, B.; Boyer, A.; BenDhia, S. Microelectronics reliability Vol. 51, num. 9-11, p. 1564-1567 DOI: 10.1016/j.microrel.2011.06.041 Data de publicació: 2011-11 Article en revista
Li, B.; Berbel, N.; Boyer, A.; BenDhia, S.; Fernandez-Garcia, R. Microelectronics reliability Vol. 51, num. 9-11, p. 1557-1560 DOI: 10.1016/j.microrel.2011.06.010 Data de publicació: 2011-10 Article en revista
This paper presents a high-bandwidth capacitance estimation and driving circuit especially tailored for its use with MEMS electrostatic actuators. The circuit can be integrated as a part of a system comprising
an electrostatic actuator to provide self-testing and failure prediction capabilities and also as a simple and
low-cost actuator dynamics characterization system capable of measuring both periodic and nonperiodic movements.
Martin, J.; Amat, Esteve; Gonzalez, M.B.; Verheyen, P.; Rodríguez, R.; Nafría, M.; Aymerich , X.; Simoen, E. Microelectronics reliability p. 1263-1266 DOI: 10.1016/j.microrel.2010.07.150 Data de publicació: 2010 Article en revista
Hot-carrier degradation in pMOS transistors with Si1–xGex implantations in the source and drain areas is analyzed (SiGe S/D). A simulation methodology is developed to translate the effects to circuit simulators. This methodology is applied to study hot-carrier degradation in CMOS inverters designed with SiGe S/D pMOS transistors. The results show that although pMOS transistors with embedded SiGe S/D have a better device performance, these devices are more sensitive to hot-carrier degradation at both the device and circuit levels.
Amat, Esteve; Rodríguez, R.; Nafría, M.; Aymerich , X.; Stathis, J.H. Microelectronics reliability Vol. 47, num. 5-7, p. 544-547 DOI: 10.1016/j.microrel.2007.01.003 Data de publicació: 2007 Article en revista
The substitution of the SiO2 gate oxide in MOS devices by a material with a high-k dielectric constant is being deeply studied nowadays to solve the problem of the leakage currents that appear with the progressive scaling of SiO2 thickness. To improve the quality of the high-k/Si interface a very thin SiO2 film is grown between both materials. In this work, HfO2/SiO2 stacks with different SiO2 thickness were subjected to different types of stress (static and dynamic) to analyze the effect of this interfacial layer of SiO2 in the degradation of the stack. The results show that the dielectric degradation depends on the stress applied and that the thickness of the SiO2 interfacial layer influences the advanced stages of the stack degradation.
In this paper we develop combinatorial methods for the evaluation of yield and operational reliability of fault-tolerant systems-on-chip. The method for yield computation assumes that defects are produced according to a model in which defects are lethal and affect given components of the system following a distribution common to all defects; the method for the computation of operational reliability also assumes that the fault-tree function of the system is increasing.
The distribution of the number of defects is arbitrary. The methods are based on the formulation of, respectively, the yield and the operational reliability as the probability that a given boolean function with multiple-valued variables has value 1. That probability is computed by analyzing
a ROMDD (reduced ordered multiple-value decision diagram) representation of the function.
For efficiency reasons, a coded ROBDD (reduced ordered binary decision diagram) representation of the function is built first and, then, that coded ROBDD is transformed into the ROMDD required by the methods. We present numerical experiments showing that the methods are able to cope with quite large systems in moderate CPU times.
Deposition of tin monoxide thin films by reactive magnetron sputtering is investigated. The analysis by XRD and XPS have proved the presence of SnO as the main compound in the layers, which also contain SnO2 and metallic Sn. A set of process parameters for the obtention of these films is found. The material, used as sensitive layer in resistive type gas sensor, shows an increase in its resistivity when exposed to vapours of ethanol (p-type conductivity).
The influence of the shape of VLSI interconnects on the lifetime due to electromigration is investigated. Simulations and experiments indicate that, in some cases, the right angle corners of the metal lines, widely interconnections layout of VLSI circuits, reduce the lifetime of such interconnects. Substitutions by more gradual, smaller angled corners improve electromigration lifetimes.