Valero-Garcia, M; Navarro, J.; Llaberia, J.; Valero, M.; Lang, T. Journal of VLSI signal processing systems for signal, image and video technology Vol. 4, num. 1, p. 7-25 DOI: 10.1007/BF00930615 Data de publicació: 1992-02 Article en revista
In this paper we present a method to implement one-dimensional Systolic Algorithms with data contraflow using Pipelined Functional Units. Some procedures are proposed which permit the systematic application of the method. The paper includes an example of application of the method to a one-dimensional systolic algorithm with data contraflow for QR decomposition.
The solution of the algebraic path problem (APP) for arbitrarily sized graphs by a fixed-size systolic array processor (SAP) is addressed. First, a block algorithm for the APP is obtained. The algorithm is modified to require only two block subproblems or primitives. Two similar SAPs are designed for solving the primitives. Then, the primitive SAPs are integrated into a versatile SAP (VSAP). The proposed VSAP has p×p processing elements (PEs), solving the APP of an n-vertex graph in n3/p2+n2/p+3p-2 cycles. With slight modifications in the operations performed by the PEs, the problem is optimally solved in n3/p2+3p-2 cycles.