The present trend of increasing speed of operation in integrated circuits may produce transmission line effects in the interconnections. To decide whether these effects are important and should be taken into account in the interconnection modelling, an evaluation of characteristic impedance and signal time propagation is needed. These two parameters are calculated from capacitance and inductance values obtained by simulation using an industrial software tool. Typical VLSI interconnection dimensions are considered, studying the influence of design variables (distance between lines and length) on the values obtained. The relative magnitude of these parameters has an effect on which interconnect model best suits a certain interconnection. Ranges of validity of the different models are given for typical cases.
Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling tendencies of IC scaling are analysed, following interest in advanced technologies. The potential for permanent errors is shown in the case of a RAM cell. A circuit-level model for the coupling mechanism is proposed. The implementation of an IC for experimentation, and the measurements obtained, are discussed