This work proposes a new fetch unit model, inspired in the trace processor . Instead of fetching instruction traces, our fetch unit will fetch instruction streams. An instruction stream is a sequential run of instructions, dened by the starting address and the stream length. All branches included in the stream are assumed to be not taken, except for the terminating one, which should be always taken (else, we are terminating the stream prematurely). We will show how stream fetching approaches the four factors determining instruction fetch performance: the width of instructions fetched per cycle, instruction cache misses, branch prediction throughput and branch prediction accuracy.
The synchronized and simultaneous access to several vectors that form a single stream occurs in SIMD vector multiprocessors as well as in MIMD superscalar multiprocessors with decoupled access. In this paper we propose a block-interleaved storage scheme and an out-oforder access mechanism that allows conflict-free access to
streams with an arbitrary initial address and constant stride
between elements. A maximal number of conflict-free
families including the most commonly used strides can be
obtained. We consider the use of a crossbar interconnection
network, although the method applies also for the case of a
multistage interconnection network.
Navarro, J.; Juan, A.; Valero, M.; Llaberia, J.; Lang, T. Newsletter - IEEE Computer Society. Technical Committee on Computer Architecture Vol. 1, num. 1, p. 10-14 Data de publicació: 1993-09 Article en revista