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Virtual-physical registers

Autor
Gonzalez, A.; González, J.; Valero, M.
Tipus d'activitat
Document cientificotècnic
Data
1997-07
Codi
UPC-DAC-1997-45
Resum
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pipeline, instead of doing it in the decode stage as conventional schemes do. In this way the register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical registers require some additional artifact to keep track of dependences. This is achieved by intro...
Paraules clau
Dynamic Register Renaming, Register Organization, Register Pressure, Dynamically Scheduled Processors
Grup de recerca
ARCO - Microarquitectura i Compiladors
CAP - Grup de Computació d'Altes Prestacions

Participants