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Hierarchical clustered register file organization for VLIW processors

Autor
Zalamea, F.; Llosa, J.; Ayguade, E.; Valero, M.
Tipus d'activitat
Document cientificotècnic
Data
2001-07
Codi
UPC-DAC-2001-21
Resum
Technology projections indicate that wire delays will become one of the biggest constraints in future microprocessor designs. To avoid long wire delays and therefore long cycle times, processor cores must be partitioned into components so that most of the communication is done locally. In this paper, we propose a novel register file organization for VLIW cores that combines clustering with a hierarchical register file organization. Functional units are organized in clusters with a local first le...
Paraules clau
Clustering, Module Scheduler, Register File Organization
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants