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Branch classification for SMT fetch gating

Autor
Knijnenburg, P.; Alex Ramirez; Larriba, J.; Valero, M.
Tipus d'activitat
Document cientificotècnic
Data
2002-09
Codi
UPC-DAC-2002-47
Resum
In Simultaneous Multithreaded architectures many separate threads are running concurrently, sharing processor resources, thereby realizing a high utilization rate of the available hardware. However, this also implies that threads are competing for resources and in many cases this competition can actually degrade overall performance. There are two major causes for this: first, instructions that because of a long latency data cache miss cause dependent instructions not to proceed for many cycles t...
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions
DAMA-UPC - Data Management Group

Participants