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A simple low-energy instruction wakeup mechanism

Autor
Ramirez, M.; Cristal, A.; Veidenbaum, A.; Villa, L.; Valero, M.
Tipus d'activitat
Article en revista
Revista
Lecture notes in computer science
Data de publicació
2003
Volum
2858
Pàgina inicial
99
Pàgina final
112
DOI
https://doi.org/10.1007/978-3-540-39707-6_8 Obrir en finestra nova
URL
https://link.springer.com/chapter/10.1007/978-3-540-39707-6_8 Obrir en finestra nova
Resum
Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hardware complexity to reduce energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a mechanism for instruction wakeup, which uses a multi-block instruction queue design. The blocks are turned off until the mechanism determines which blocks to access on wakeup using...
Paraules clau
Superscalar Processors, Out Of Order Execution, Instruction Window, Instruction Wake Up, Low Power, Cam
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants