Carregant...
Carregant...

Vés al contingut (premeu Retorn)

Power-performance trade-offs in wide and clustered VLIW cores for numerical codes

Autor
Pericas, M.; Ayguade, E.; Zalamea, J.; Llosa, J.; Valero, M.
Tipus d'activitat
Article en revista
Revista
Lecture notes in computer science
Data de publicació
2003-10
Volum
2858
Pàgina inicial
113
Pàgina final
126
DOI
https://doi.org/10.1007/978-3-540-39707-6_9 Obrir en finestra nova
URL
http://link.springer.com/chapter/10.1007%2F978-3-540-39707-6_9 Obrir en finestra nova
Resum
Instruction-Level Parallelism (ILP) is the main source of performance achievable in numerical applications. Architecturalresources and program recurrences are the main limitations to the amount of ILP exploitable from loops, the most time-consuming part in numerical computations. In order to increase the issue rate, current designs use growing degrees of resource replication for memory ports and functional units. But the high costs in terms of power, area and clock cycle of this technique are ma...
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants