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Software trace cache

Autor
Alex Ramirez; Larriba, J.; Valero, M.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on computers
Data de publicació
2005-01
Volum
54
Número
1
Pàgina inicial
22
Pàgina final
35
DOI
https://doi.org/10.1109/TC.2005.13 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/103093 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/1362637/ Obrir en finestra nova
Resum
We explore the use of compiler optimizations, which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying hardware resources regardless of the specific details of the processor/architecture in order to increase fetch performance. The Software Trace Cache (STC) is a code layout algorithm with a broader target than previous layout optimizations. We target not only an improvement in the instruction cache hit rate, but also an increase i...
Citació
Ramírez, A., Larriba, J., Valero, M. Software trace cache. "IEEE transactions on computers", Gener 2005, vol. 54, núm. 1, p. 22-35.
Paraules clau
Branch prediction, Compiler optimizations, Instruction fetch, Pipeline processors, Trace cache
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions
DAMA-UPC - Data Management Group

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