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A detailed analysis and electrical modeling of gate oxide shorts in mos transistors

Autor
Segura, J.; Benito, C.; Rubio, A.; Hawkins, C.
Tipus d'activitat
Article en revista
Revista
Journal of electronic testing. Theory and applications
Data de publicació
1996-06
Volum
8
Número
3
Pàgina inicial
229
Pàgina final
239
DOI
https://doi.org/10.1007/BF00133386 Obrir en finestra nova
URL
http://link.springer.com/article/10.1007%2FBF00133386 Obrir en finestra nova
Resum
The characteristics of devices with gate oxide short defects are investigated for both n-MOS and p-MOS transistors. Experimental results obtained from real and design induced gate oxide shorts are presented analyzing the defect-induced conduction mechanisms that determine the transistor behavior. It is shown that three variables (defect location, transistor type and gate polysilicon doping type) influence the characteristics of a defective device. Of interest is the prediction and observation of...
Paraules clau
Fault Modeling, Gate Oxide Short, Physical Defects
Grup de recerca
HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions

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