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Impact of gate tunnelling leakage on CMOS circuits with full open defects

Autor
Rodriguez-Montanes, R.; Arumi, D.; Figueras, J.; Eichenberger, S.; Hora, C.; Kruseman, B.
Tipus d'activitat
Article en revista
Revista
Electronics Letters
Data de publicació
2007-10
Volum
43
Número
21
Pàgina inicial
1140
Pàgina final
1141
DOI
https://doi.org/10.1049/el:20072117 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/20118 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/search/srchabstract.jsp?arnumber=4349252&isnumber=4349241&punumber=2220&k2dockey=4349252@ieejrns&query=%28%28arume%29%3Cin%3Emetadata+%29&pos=0 Obrir en finestra nova
Activitat premiada
Si
Resum
Electronics Letter of the Month Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented. Interco...
Citació
Rodriguez, R. [et al.]. Impact of gate tunnelling leakage on CMOS circuits with full open defects. "Electronics Letters", Octubre 2007, vol. 43, núm. Issue 21, p. 1140-1141.
Grup de recerca
CRnE - Centre de Recerca en Ciència i Enginyeria Multiescala de Barcelona
QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat

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