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Dynamic code partitioning for clustered architectures

Autor
Canal, R.; Parcerisa, Joan-Manuel; Gonzalez, A.
Tipus d'activitat
Article en revista
Revista
International journal of parallel programming
Data de publicació
2001-02
Volum
29
Número
1
Pàgina inicial
59
Pàgina final
79
DOI
https://doi.org/10.1023/A:1026483904675 Obrir en finestra nova
Resum
Recent works show that delays introduced in the issue and bypass logic will become critical for wide issue superscalar processors. One of the proposed solutions is clustering the processor core. Clustered architectures benefit from a less complex partitioned processor core and thus, incur less critical delays. We propose a dynamic instruction steering logic for these clustered architectures that decides at decode time the cluster where each instruction is executed. The performance of clustered a...
Paraules clau
Floating Point Arithmetic, Formal Logic, Instruction Sets, Parallel Architectures
Grup de recerca
ARCO - Microarquitectura i Compiladors
VIRTUOS - Virtualisation and Operating Systems