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Improving latency tolerance of multithreading through decoupling

Autor
Parcerisa, Joan-Manuel; Gonzalez, A.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on computers
Data de publicació
2001-10
Volum
50
Número
10
Pàgina inicial
1084
Pàgina final
1094
DOI
https://doi.org/10.1109/12.956093 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/96788 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/956093/ Obrir en finestra nova
Resum
The increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, designed over a superscalar core, are therefore directly concerned by this problem. The article presents and evaluates a novel processor microarchitecture which combines two paradigms: simultaneous multithreading and access/execute decoupling. Since its decoupled units issue instru...
Citació
Parcerisa, Joan-Manuel, González, A. Improving latency tolerance of multithreading through decoupling. "IEEE transactions on computers", Octubre 2001, vol. 50, núm. 10, p. 1084-1094.
Paraules clau
Access/execute Decoupling, Latency Hiding, Instruction-level Parallelism, Hardware Complexity
Grup de recerca
ARCO - Microarquitectura i Compiladors

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