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On-chip interconnects and instruction steering schemes for clustered microarchitectures

Autor
Parcerisa, Joan-Manuel; Sahuquillo, J.; Gonzalez, A.; Duato, J.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on parallel and distributed systems
Data de publicació
2005-02
Volum
16
Número
2
Pàgina inicial
130
Pàgina final
144
DOI
https://doi.org/10.1109/TPDS.2005.23 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/100490 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/1374854/ Obrir en finestra nova
Resum
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection networks for clustered superscalar microarchitectures. This new class of interconnects has demands and characteristics different from traditional multiprocessor networks. In particular, in a clustered microarchitecture, a low intercluster communication latency is essential ...
Citació
Parcerisa, J.M., Sahuquillo, J., González, A., Duato, J. On-chip interconnects and instruction steering schemes for clustered microarchitectures. "IEEE transactions on parallel and distributed systems", Febrer 2005, vol. 16, núm. 2, p. 130-144.
Paraules clau
Clustered Microarchitecture, Complexity, Instruction Steering, Intercluster Communication, On-chip Interconnects
Grup de recerca
ARCO - Microarquitectura i Compiladors

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