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Vectorized register tiling

Autor
Berna, A.; Jimenez, M.; Llaberia, J.
Tipus d'activitat
Document cientificotècnic
Data
2012-01
Codi
UPC-DAC-RR-CAP-2012-4
Repositori
http://hdl.handle.net/2117/16308 Obrir en finestra nova
URL
https://www.ac.upc.edu/app/research-reports/html/2012/5/abstractAndPoster.pdf Obrir en finestra nova
Resum
In the last years, there has been much effort in commercial compilers (icc, gcc) to exploit efficiently the SIMD capabilities and the memory hierarchy that the current processors offer. However, the small numbers of compilers that can automatically exploit these characteristics achieve in most cases unsatisfactory results. Therefore, the programmers often need to apply by hand the optimizations to the source code, write manually the code in assembly or use compiler built-in functions (such intri...
Citació
Berna, A.; Jimenez, M.; Llaberia, J. "Vectorized register tiling". 2012.
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

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